Acceleration, power reduction, reliability and low-overhead are four major goals of neural networks. Residue number systems (RNS) intuitionally can improve all of the goals simultaneously. Especially for reliability-critical applications, the generic ability of modularization empowers the redundant RNS (RRNS) fault tolerance. However, the RRNS still suffers four critical issues including dynamic range (DR), sign detection, limited efficient moduli, and redundancy-decoding complexity. In this paper, we apply the piecewise linear units to limit the DR of next layer, stored sign-and-parity bits to make sign detection efficient, the hierarchical structure to make the best of efficient moduli, and the AN-codes for both sub-RNS error cor-rection and MMR checking. An expanded residue-to-binary converter is developed for highly reduction of the whole multi-ple-module redundancy decoder. This is the first paper to incor-porate AN codes to the RRNS applied in highly-reliable neural networks. From our evaluation under approximately equal bit-length L of moduli in a DR of hkL bits, the$g=(hk+2)(hk+1)/2$residue-to-binary converters and g(g-1)/2 comparators in the conventional RRNS can be reduced to an expanded residue-to-binary converter with only k decoders. From the BLER anal-yses, more than 126 times of MTBF can be achieved.

Neural networks play a key role in modern AI accelerators, in which acceleration and power reduction have been two known issues. When human lives may be threatened by accidents due to a wrong decision, the reliability bursts out far beyond other issues of the AI accelerators in automotive chips. Although input-side deep layers have been shown to possess considerable self-healing, arithmetic faults in shallow decision layers may still cause unimaginable catastrophe. This motivates us to develop a synthesis system called TAIWAN Online for testing AI with AN codes online. TAIWAN Online takes a trained model with a Keras-like format and the accuracy resolution for predicting a suitable subsystem. For low-resolution datasets, a ternary-coded-binarized neural network called TCBNN is proposed for approximate computing, where AN codes are adopted for arithmetic-weight error correction. While for high-resolution datasets, redundant residue number systems are applied for parallelized acceleration, and AN codes are utilized as AN-RRNS for self-checking in efficient multiple residue-modular redundancies, MMR. Briefly pointing out the key contributions, a k-moduli AN-RRNS can highly reduce the time-area product of MMR decoders from O(k4) of state-of-the-art RRNSs to only one. While the TCBNN can have fewer synapses than any regular-weight-quantized BNNs. From experimental results for a neuron-based block, the MTBF can be improved up to 126 times in the proposed infection-rate model.

Neural Network suffers four major issues including acceleration, power consumption, area overhead and fault tolerance. In this paper we develop a systematic approach to design a low-power, compact, fast and reliable neural network based on a redundant residue number system. Residue number systems have been applied in designing neural network except the CORDIC-based activation functions including hypertangent, logistic and softmax functions. This issue results in that the entire neural network cannot be totally self-checked and extra operations make the time, power and area reductions wasted. In our systematic approach we propose some design rules for ensuring the checking rate without loss of reductions in time, area and power consumption. From experiments on three neu-ral network with 24-bit fixed-point operations for the MNIST handwritten digit data set, 3, 4, and 5 moduli are separately employed for achieving all balanced improvements in power-saving, area-reduction, speed-acceleration and reliability pro-motion. Experimental results show that all the power, time and area can be reduced to only about one third, and the entire network in any combination of software and hardware can be self-checked in an aliasing rate of only 0.39% and TMR-correctable under the single-residue fault model.

Neuromorphic RRAM has become the most promising candidate for AI applications. But it suffers three issues including degradation, defects and errors. To overcome the three issues we proposed a precompensation technique for compensating resistive degradation. A linear-system-based BIST architecture is developed with proposed diagonal sliding march test can effectively and efficiently screen out the uncompensated degradation and permanent defects. Analog Berger codes is proposed for detecting transient errors for variation learning and self-checking for asymmetric errors. From evaluations, the precompensation takes only 5/B time for batch operations of B cycles. Proposed BIST approach and method can reduced 2LN march tests to 6N for L-level RRAMs. The self-healing ability is verified by analog-Berger-code error detection. From experiments using a typical neural network for MNIST handwritten digit dataset the network can be healed with only 2% of accuracy and about 35% of training steps.

A novel memory repair architecture based on redundant hypercube is proposed, which mainly consists of a modified ternary CAM with an address bubble-shifter. Generally for an acceptable repair rate about 3% of spare sub cubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential Cube Pivoting algorithm are also developed for redundancy analysis. Almost 100% of repair rate can be obtained using only 32 equivalent rows under reasonable situations. Under less spare memory the repair rates of proposed approaches can be much higher than most results of previous work.

Digital synchronous mirror delaylines can lock in only two cycles and make burst and sleep modes feasible for high-speed and low-power applications. Conventional digital synchronous mirror delay usually spends at least one delay line with a length comparable to the resolution. The area overhead becomes an issue in multiple-module circuits. The objective of this paper is thus to reduce the area overhead by folding the delayline. Simple corollaries from the congruence theorem are derived for function proves. Experimental results show that the proposed design can save more than 75% of area overhead for fixed skew compensation of hundreds of stages under acceptable phase errors.

Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes. The clock and data input capacitances of a latch are assumed the same as that of a regular gate. A double-latch FF thus consumes 5 transitions including the interconnection between latches when the data changes.

Presents a novel scan architecture for low-power testing, which employs the techniques of multiphase clocking, token ring, and clock-gating. When the multiphase clocking technique is directly employed to a scan chain, inter-phase skews and large routing area will be the problems. We develop a token scan cell design to address these problems. To reduce the power dissipation due to the clock and scan-in data trees, we propose a novel clock-gating technique that takes advantage of the regularity and periodicity of the token scan chain. Combining the three techniques, the token scan architecture can efficiently reduce the data transitions in the scan circuits as well as the switching activity in both the clock and the scan-in data trees. From experiments, more than 95% of power reduction can be achieved for most circuits with long scan chains.

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application time. The basic idea is to identify an input control pattern (CP) for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be reduced or even eliminated. A D-algorithm-like CP generator is developed to generate the CP. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve 22.37% of average improvement by redoing the experiments in previous work using our test sets, while 34.23% average improvement can be achieved if the input control technique is employed after the latch ordering and vector ordering techniques.

This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power. This method can be efficiently employed in a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. The improvement percentage can be up to 50% when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, 76% of peak-power reduction can be achieved.

This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and the latch ordering techniques.

This paper presents BIFEST, an ATPG system that employs the built-in intermediate voltage test technique in an efficient ATPG process to deal with CMOS bridging faults. Fast and accurate calculations of the intermediate bridging voltages and the variant threshold tolerance margins on a resistive bridging fault model are presented. A PODEM-like, PPSFP-based ATPG process is developed to generate test patterns for faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits, called built-in intermediate voltage sensors (BIVSs). By this methodology, almost the same fault coverage as that employingIDDQtesting can be achieved with only logic monitoring required.

Recently the bulk-driven current mirror technique has been employed in built-in current sensors for low voltage environment. This paper proposes 4 arrangements of built-in current sensors based on this technique. They are mainly different in biasing schemes end respectively take the advantages of simplicity, accuracy, flexibility and low power dissipation. From experiments, these sensors have small performance impact which causes only 0.3 V of power supply voltage drop and 0.3 ns delay of circuit speed degradation. These sensors require single external power supply and small area overhead.

This paper presents the BIFEST, an ATPG system that combines the conventional ATPG process and the built-in intermediate voltage test technique to deal with CMOS bridging faults. A PODEM-like, PPSFP-based ATPG process that can effectively and efficiently model the bridging fault effects is developed to process those faults that are conventionally logic-testable. The remaining faults are then dealt with by special circuits called built-in intermediate voltage sensors. By this methodology almost the same fault coverage as that employing IDDQ testing can be achieved with only logic monitoring required.