This paper introduces an efficient new 4:1 compressor that uses carry disregard and OR-based approximation, leading to the development of 13 approximate unsigned multipliers. The proposed multipliers, 8-bit array-comPressor oR-based carry dIsregard Multipliers (PRIM8s) demonstrate significant improvements in area, power, delay, and Power-Delay-Product (PDP) by an average of 29%, 31%, 25%, and 47%, compared to the exact multiplier. In the approximate multiplier literature, with our hardware, we establish new Pareto fronts for most criteria. The effectiveness of the proposed multipliers for noise reduction is demonstrated in an image-processing application using a low-pass Gaussian filter. On average, PRIM8s reduce power consumption and improve speed by 32.36% and 19.01% compared to the exact multiplier, while also enhancing image quality, as indicated by a 0.14% increase in Structural Similarity Index Measure (SSIM).

Coarse-grained Reconfigurable Architectures (CGRAs) offer energy efficiency and programmability, making them integral to modern high-performance computing. However, complicated compilation when mapping the Dataflow Graph (DFG) to CGRA components leads to significant time overhead, area inefficiency, and routing challenges, especially for large-scale applications today. In this article, a fast and accurate DFG mapping approach called PRISA is proposed to reduce the compilation delay and obtain mapping solutions with higher qualities in a more reasonable time. This approach analytically identifies the potential and weak regions in the space of mapping solutions to guide the search algorithm and prevent ineffective examinations. Moreover, using the potential solutions and a novel sparse matrix permutation technique, we introduced Selective Initial Solution (SIS) to further improve the performance of PRISA without needing long-time optimizations. As the computational requirements in the PRISA are performed analytically, there is no additional time overhead. We conducted extensive experiments on the benchmark graphs of CGRA-ME and VPR-8 toolkits and obtained outstanding results compared to integer linear programming, evolutionary, and graph traversal approaches in terms of compilation time and mapping communication cost. Our approach could map the DFGs of VPR-8 toolkit with 3.64 maximal FIFO size requirement and 53.5 ms time overhead, on average.

The demand for energy-efficient and high-performance embedded systems drives the evolution of new hardware architectures, including concepts like approximate computing. This paper presents a novel reconfigurable embed-ded platform named “phoeniX”, using the standard RISC-V ISA, maximizing energy efficiency while maintaining acceptable application-level accuracy. The platform enables the integration of approximate circuits at the core level with diverse structures, accuracies, and timings without requiring modifications to the core, particularly in the control logic. The platform introduces novel control features, allowing configurable trade-offs between accuracy and energy consumption based on specific application requirements. To evaluate the effectiveness of the platform, experiments were conducted on a set of applications, such as image processing and Dhrystone benchmark. The core with its original execution engine, occupies 0.024mm2 of area, with average power consumption of 4.23m W at 1.1 V operating voltage, average energy-efficiency of 7.85pJ per operation at 620MHz frequency in 45nm CMOS technology. The configurable platform with a highly optimized 3-stage pipelined RV32I(E)M architecture, possesses a DMIPS/MHz of 1.89, and a CPI of 1.13, showcasing remarkable capabilities for an embedded processor.

This paper presents the design and development of Signed Carry Disregard Multiplier (SCDM8), a family of signed approximate multipliers tailored for integration into Convolutional Neural Networks (CNNs). Extensive experiments were conducted on popular pre-trained CNN models, including VGG16, VGG19, ResNet101, ResNet152, MobileNetV2, InceptionV3, and ConvNeXt-T to evaluate the trade-off between accuracy and approximation. The results demonstrate that ACE-CNN outperforms other configurations, offering a favorable balance between accuracy and computational efficiency. In our experiments, when applied to VGG16, SCDM8 achieves an average reduction in power consumption of 35% with a marginal decrease in accuracy of only 1.5%. Similarly, when incorporated into ResNet152, SCDM8 yields an energy saving of 42% while sacrificing only 1.8% in accuracy. ACE-CNN provides the first approximate version of ConvNeXt which yields up to 72% energy improvement at the price of less than only 1.3% Top-1 accuracy. These results highlight the suitability of SCDM8 as an approximation method across various CNN models. Our analysis shows that the ACE-CNN outperforms state-of-the-art approaches in accuracy, energy efficiency, and computation precision for image classification tasks in CNNs. Our study investigated the resiliency of CNN models to approximate multipliers, revealing that ResNet101 demonstrated the highest resiliency with an average difference in the accuracy of 0.97%, whereas LeNet5 Inspired-CNN exhibited the lowest resiliency with an average difference of 2.92%. These findings aid in selecting energy-efficient approximate multipliers for CNN-based systems, and contribute to the development of energy-efficient deep learning systems by offering an effective approximation technique for multipliers in CNNs. The proposed SCDM8 family of approximate multipliers opens new avenues for efficient deep learning applications, enabling significant energy savings with virtually no loss in accuracy.

Abstract In 2018, Abbasinezhad‐Mood and Nikooghadam (IEEE Transaction on Smart Grid, pp 6194–6205, 9(6), 2018) proposed an ultra‐lightweight secure scheme for neighbourhood area network () communications in smart grid. They have claimed that their protocol is secure against all known attacks in environment by providing informal security analysis besides a formal analysis which was done by using an automatic verification tool. However, by performing several attacks, this study shows that their scheme has serious security flaws. After performing each attack, lightweight countermeasures is proposed for securing their protocol against that attack.

Several challenges in improving the performance of computing systems have given rise to emerging computing paradigms. One of these paradigms is approximate computing. Many applications require different levels of accuracy and are error-tolerance to a certain degree. Approximate computations can reduce the calculation complexities significantly and thus improve the performance. Here, we propose a methodology for designing approximate N-bit array multipliers based on carry disregarding. We evaluate and analyze the proposed multipliers both experimentally and theoretically. The proposed 8-bit multipliers, compared to the exact multiplier, reduce the critical path delay, power consumption, and area by 29%, 29%, and 30%, on average. Compared to the existing approximate array architectures in the literature, they have improved 14.3%, 22.8%, and 26.4%, respectively. Compared to the exact 16-bit multiplier, the proposed 16-bit multipliers have reduced the delay, power consumption, and area by 35%, 24%, and 23% on average. In an image processing application, we have also demonstrated the applicability of a wide range of proposed multipliers, which have Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) over 30 dB and 94%, respectively.

Nowadays, a wide range of applications can tolerate certain computational errors. Hence, approximate computing has become one of the most attractive topics in computer architecture. Reducing accuracy in computations in a premeditated and appropriate manner reduces architectural complexities, and as a result, performance, power consumption, and area can improve significantly. This paper proposes a novel approximate multiplier design. The proposed design has been implemented using 45 nm CMOS technology and has been extensively evaluated. Compared to existing approximate architectures, the proposed approximate multiplier has higher accuracy. It also achieves better results in critical path delay, power consumption, and area up to 47.54 %, 75.24%, and 92.49%, respectively. Compared to the precise multipliers, our evaluations show that the critical path delay, power consumption, and area have been improved by 39%, 18%, and 6 %, respectively.

Due to the ever-increasing complexity of computing tasks, emerging computing paradigms that increase efficiency, such as approximate computing, are gaining momentum. However, so far, the majority of proposed solutions for hardware-based approximation have been application-specific and/or limited to smaller units of the computing system and require engineering effort for integration into the rest of the system. In this paper, we present Approximate and Exact Multi-Processor system-on-chip (AxE) platform. AxE is the first general-purpose approximate Multi-Processor System-on-Chip (MPSoC). AxE is a heterogeneous RISC-V platform with exact and approximate cores that allows exploring hardware approximation for any application and using software instructions. Using the full capacity of an entire MPSoC, especially a heterogeneous one such as AxE, is an increasingly challenging problem. Therefore, we also propose a task mapping method for running exact and approximable applications on AxE. That is a mixed task mapping, in which applications are viewed as a set of tasks that can be run independently on different processors with different capabilities (exact or approximate). We evaluated our proposed method on AxE and reached a 32% average execution speed-up and 21% energy consumption saving with an average of 99.3% accuracy on three mixed workloads. We also ran a sample image processing application, namely gray-scale filter, on AxE and will present its results.

The divisible load scheduling of image processing applications on the heterogeneous star network is addressed in this paper. In our platform, processors and links have different speeds. Also the computation and communication overheads are considered. A new genetic algorithm for minimizing the processing time of low level image applications using divisible load theory is introduced. A closed form solution for the processing time and the image fractions that should be assigned to each processor are obtained. The optimum number of participating processors and the optimal sequence for load distribution with a new genetic algorithm are derived. The effect of different image and kernel sizes on processing time and speed up are investigated. Finally, to indicate the efficiency of our algorithm, several numerical experiments are presented.

Multipath (MP) interference in urban canyons is one of the major sources of the positioning error. Among different methods for MP mitigation, vectorised receiver (VR) is a promising one in which channels can share their information, and as a result the stronger channels can aid the weaker or affected ones to be tracked more accurately. This study proposes a weighted VR (WVR) with the strategy of giving more weights to the observations with lower vulnerability to MP. To increase the number of immune satellites to MP, global positioning system, and global navigation satellite system integration in WVR has been discussed. The performance is also compared with conventional VR. The experimental results show that the proposed method both in a static mode under an exaggerated MP condition and in a drive through an urban canyon could find the position, respectively, with about 10 and 13% improvements.

In 2010, Fan et al. proposed a Smart Card-Based Authenticated Key Exchange protocol with CAPTCHAs for wireless mobile networks. In this paper, it is shown that their proposed protocol is vulnerable to Key Compromise Impersonation (KCI) and ephemeral key compromise impersonation attacks while it does not provide the key confirmation attribute. Furthermore, it is inefficient due to number redundancy of rounds and computational costs. To overcome these weaknesses, two secure and efficient smart card-based Authenticated Key Exchange (AKE) protocols combined with CAPTCHAs are proposed for wireless mobile networks that provide many security attributes while they have a remarkable efficiency when compared with Fan et al.'s protocol in the terms of communication costs and computational complexities.

Reconfiguration overhead is an important obstacle that limits the performance of on-line scheduling algorithms in reconfigurable computing systems and increases the overall execution time. Configuration reusing (task reusing) can decrease reconfiguration overhead considerably, particularly in periodic applications. In this paper, we present a new approach for on-line scheduling and placement in which configuration reusing is considered as a main characteristic in order to reduce reconfiguration overhead and decrease total execution time of the tasks. A large variety of experiments have been conducted on the proposed algorithm. Obtained results show considerable improvement in overall execution time of the tasks.

The phishing as an online identity theft is one of the fastest growing crimes in the Internet. Several counter-measures are proposed through the years, one of them is the Anti-phishing Authentication (APA) protocol that is based on SPEKE which is a Password Authenticated Key Exchange (PAKE) protocol. In this paper, it is shown that the APA protocol is vulnerable to password compromise impersonation, ephemeral key compromise impersonation and malicious server attacks. An improved anti-phishing protocol is also proposed that provides several security attributes including mutual authentication, forward secrecy, known session key security, no key control, Key confirmation, and resilience to Denning-Sacco, password compromise impersonation, Unknown Key Share (UKS), off-line dictionary, undetectable online dictionary, ephemeral key compromise impersonation, Key Compromise Impersonation (KCI), eavesdropping, message loss, message modification, message insertion and message replay attacks while it provides better efficiency when compared with the APA protocol.

Reconfigurable systems have become very popular because of their impact in increasing performance improvement for executing a number of applications such as morphology, image compression, etc. These systems provide a general platform for executing applications. However, effectively using the full potential of these systems cars be challenging without the knowledge of the system's performance characteristics. A general analytical model is developed in this paper for reconfigurable computing systems based on queuing theory. The reconfigurable system is composed of a host processor coupled with a reconfigurable hardware such as an FPGA.

There are three main irreducible polvnomials used,for daigning Galois Field nrultiplierr whicli are: all-one polvnon~ial (AOP), equallv spaced poivnomial (ESP) and irreducible trinomial. Althougli using these polvnomials causes low space and lime complexih, in the rntrltiplier archifechrre, the.v do not exist.fir many field degrees. It has been shown that an irreducible penranomial exists whenever an irreducible trinomial does not exist for a peld degree. Therefire, using pentanomia1.v in designing multipliers have practical importance. In this paper the Mashovito mtrltiplier using general irredtrcible pentano~nials is considered This can be used in impletnenting multipliers based on any h,pe of pentanomial. Then some special h,pes of pentanomials are introduced which reduce the number of XOR gates and/or de1a.v in the Mastrovito tnultiplier

Nowadays, the reliability and correctness of digital circuits has become increasingly important. In addition, digital systems design methodology has been changing to HDL-based design. Thus the test methods which are based on behavioral level design would be broadly applicable. The other factor primarily influencing the practical field of application of a specific test generation algorithm is the computational complexity of the algorithm. Random test pattern generation algorithms are much simple than the other types of algorithms. Hence, developing such algorithms is exceedingly beneficial. In this paper, an extension to random test pattern generation is proposed which makes it semi-algorithmic, so it is called SAT. SAT generates some parts of test vectors deterministically for the conditional nodes of the circuit’s CFG extracted from VDHL code. Simulation shows the quality of SAT generated test sets, according to path coverage, is better than ones produced by uniformly random test pattern generation.

Routing algorithms in wireless sensor networks have attracted much attention during recent years. Due to the limited resources of each sensor node, e.g. limited power supply and limited communication bandwidth, routing algorithm in such networks will be complex and affect the system performance and its lifetime. In this paper the area, which sensor laid out, is partitioned into some regions. Each region, which contains some sensors, is considered as a node of a Mesh. The nodes can communicate to their neighbor nodes through a number of virtual channels. Each virtual channel formed by connecting two sensors to adjacent regions that are located in Radio-range of each other. Simulation results show that the proposed algorithm (MBR) can be used to optimize the use of the network resources and reduce the power consumption of the network.