Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Ashok Kumar Palaniswamy

dblp:20/8110 · DBLP profile ↗
← Back
5ranked-venue papers
5as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 5 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Integrated circuit design · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.212016
ATPG for Delay Defects in Current Mode Threshold Logic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Electronic design automation › hardware verification and test
test generation
0.212016
ATPG for Delay Defects in Current Mode Threshold Logic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Integrated circuit design › digital circuit design › threshold logic
threshold logic circuits
0.112016
ATPG for Delay Defects in Current Mode Threshold Logic Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016

Methods — techniques the papers use, named apart from their topics

delay fault excitation · 0.2current-mode threshold logic · 0.2
YearPublicationVenuePosition
2016 ATPG for Delay Defects in Current Mode Threshold Logic Circuits
abstract
An automatic test pattern generation approach to detect delay defects in a circuit consisting of current mode threshold logic gates is introduced. Each generated pattern should excite the maximum propagation delay at the fault site. Manufactured weights may vary, and maximum delay is ensured by applying an appropriately generated set of patterns per fault. Experimental results show the efficiency of the proposed methods.
Ashok Kumar Palaniswamy, Spyros Tragoudas, Themistoklis Haniotakis
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1
2014 Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms
abstract
Existing threshold logic synthesis methods decompose larger input functions into smaller input functions and perform synthesis for them. It is shown that significantly larger input functions can be synthesized by implementing the existing methods in an implicant-implicit manner. Experimental results on the ISCAS 85 benchmarks show that this impacts the synthesis cost, which drops significantly. More specifically, as the size of the functions that can be handled by the synthesis algorithm increases, the number of threshold logic gates required to implement very large input functions decreases. In addition, the total weight decreases and the performance is improved.
Ashok Kumar Palaniswamy, Spyros Tragoudas
ACM J. Emerg. Technol. Comput. Syst.1
2012 A scalable threshold logic synthesis method using ZBDDs
abstract
A scalable synthesis method for large input threshold logic circuits using Zero Suppressed Binary Decision Diagrams is introduced. Existing synthesis methods require that a large input function must be initially decomposed using small input functions and this impacts the synthesis cost. The presented approach in this paper does not consider such restrictions. It is experimentally shown that the proposed method can synthesize the primary outputs of existing benchmarks without consulting the net-list, and the synthesis cost is significantly reduced over the existing methods.
Ashok Kumar Palaniswamy, Spyros Tragoudas
ACM Great Lakes Symposium on VLSI1
2012 An efficient heuristic to identify threshold logic functions
abstract
A fast method to identify the given Boolean function as a threshold function with weight assignment is introduced. It characterizes the function based on the parameters that have been defined in the literature. The proposed method is capable to quickly characterize all functions that have less than eight inputs and has been shown to operate fast for functions with as many as forty inputs. Furthermore, comparisons with other existing heuristic methods show huge increase in the number of threshold functions identified, and drastic reduction in time and complexity.
Ashok Kumar Palaniswamy, Spyros Tragoudas
ACM J. Emerg. Technol. Comput. Syst.1
2010 Scalable identification of threshold logic functions
abstract
This paper presents a scalable method to determine that a Boolean function is a threshold logic function. When the number of inputs of the function increases, identifying a threshold logic function is a laborious task. It is shown experimentally that the proposed method is faster and identifies more threshold logic functions with weight assignment than any other existing method.
Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas
ACM Great Lakes Symposium on VLSI1