To enhance the visual quality of an image that is degraded by uneven light, an effective method is to estimate the illumination component and compress it. Some previous methods have either defects of halo artifacts or contrast loss in the enhanced image due to incorrect estimation. In this paper, we discuss this problem and propose a novel method to estimate the illumination. The illumination is obtained by iteratively solving a nonlinear diffusion equation. During the diffusion process, surround suppression is embedded in the conductance function to specially enhance the diffusive strength in textural areas of the image. The proposed estimation method has the following two merits: 1) the boundary areas are preserved in the illumination, and thus halo artifacts are prevented and 2) the textural details are preserved in the reflectance to not suffer from illumination compression, which contributes to the contrast enhancement in the result. Experimental results show that the proposed algorithm achieves excellent performance in artifact removal and local contrast enhancement.

This brief presents a fast sign detection algorithm for the residue number system moduli set {2n+1- 1, 2n- 1, 2n}. First, a sign detection algorithm for the restricted moduli set is described. The new algorithm allows for parallel implementation and consists exclusively of modulo 2nadditions. Then, a sign detection unit for the moduli set {2n+1- 1, 2n- 1, 2n} is proposed based on the new sign detection algorithm. The unit can be implemented using one carry save adder, one comparator and one prefix adder. The experimental results demonstrate that the proposed circuit unit offers 63.8%, 44.9%, and 67.6% savings on average in area, delay and power, respectively, compared with a unit based on one of the best sign detection algorithms.

The main components of an artificial neuron are adders and multipliers. In order to implement neural network, large number of adders and multipliers are required. The efficient architectures for diminished-1 modulo 2n+1 multipliers are described. The results and operands of the new modulo 2n+1 multipliers use the diminished-1, avoiding n+1 bit circuit. And the presented multipliers can handle zero inputs and results. The proposed modulo 2n+1 multiplier are built using three major functional modules, partial products generation block, partial products reduction block and a final diminished-1 adder block. The final modulo 2n+1 addition block is built around a sparse carry computation unit for the analytical and experimental results. And this indicates that the significant area and power of the proposed multipliers is superior to the earlier proposals, with a high operation speed.