Demo Data from EDBT 2026 / reviewers in the wild / expert
Ankit Choudhary
dblp:200/1086
· DBLP profile ↗
2ranked-venue papers
2as first author
1since 2021 · last 2023
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Software testing · 50% Concurrent programming · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming
concurrency bugs |
0.3 | 1 | 2017 | Efficient detection of thread safety violations via coverage-guided generation of concurrent tests · ICSE 2017 |
Software testing › concurrency testing
concurrent test generation |
0.3 | 1 | 2017 | Efficient detection of thread safety violations via coverage-guided generation of concurrent tests · ICSE 2017 |
Methods — techniques the papers use, named apart from their topics
coverage-guided test generation · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | FPGA Accelerated Bi-Cubic Convolution for Image InterpolationabstractBi-cubic Convolution (BCC) is the extensively used image interpolation technique for data-intensive applications, such as Remote Sensing satellite optical data processing realized by performing a large number of Multiply Accumulate (MAC) operations. This paper presents a novel and efficient deeply-pipelined hardware architecture for the BCC image interpolation technique, involving streaming of input image tile-wise to reduce on-chip memory footprints and utilization of FIFOs to orchestrate the data movement between on-chip memory and the computation module (CM). Data fetching and computations are performed simultaneously, enabling double buffering and significant latency improvements. The design is implemented on an Intel Arria 10 GX 1150 FPGA attaining a frequency of 186 MHz. It achieved an overall throughput of 514 frames per second (FPS) while running on an input tile of size 256×256 with 2x scaling. The obtained computational latency is 91.39 µs, providing a speedup of 23x over CPU, 4.2x over GPU, and about 12x over existing state-of-the-art FPGA implementations. Ankit Choudhary, S. K. Vaibhav Kodavati, B. Mythili, R. V. G. Anjaneyulu, Manju Sarma M |
HiPC | 1 |
| 2017 | Efficient detection of thread safety violations via coverage-guided generation of concurrent testsabstractAs writing concurrent programs is challenging, developers often rely on thread-safe classes, which encapsulate most synchronization issues. Testing such classes is crucial to ensure the correctness of concurrent programs. An effective approach to uncover otherwise missed concurrency bugs is to automatically generate concurrent tests. Existing approaches either create tests randomly, which is inefficient, build on a computationally expensive analysis of potential concurrency bugs exposed by sequential tests, or focus on exposing a particular kind of concurrency bugs, such as atomicity violations. This paper presents CovCon, a coverage-guided approach to generate concurrent tests. The key idea is to measure how often pairs of methods have already been executed concurrently and to focus the test generation on infrequently or not at all covered pairs of methods. The approach is independent of any particular bug pattern, allowing it to find arbitrary concurrency bugs, and is computationally inexpensive, allowing it to generate many tests in short time. We apply CovCon to 18 thread-safe Java classes, and it detects concurrency bugs in 17 of them. Compared to five state of the art approaches, CovCon detects more bugs than any other approach while requiring less time. Specifically, our approach finds bugs faster in 38 of 47 cases, with speedups of at least 4x for 22 of 47 cases. Ankit Choudhary, Shan Lu 0001, Michael Pradel |
ICSE | 1 |