This paper introduces a novel fault model, named defect-based hold-time fault, to represent the criteria of detecting an intra-cell defect that may cause a hold-time violation, where the detection criteria include one or more pairs of an input condition at the defective instance and a designated short path for sensitization. A novel framework is also proposed to automatically extract the defect-based hold-time faults from a targeted design based on its timing-analysis result and the pre-characterized defect-induced accelerations on the adopted cell library. Compared to conventional path-based hold-time faults, our defect-based hold-time faults can precisely describe the criteria for detecting hold-time defects and hence result in a higher defect coverage with a smaller pattern set. Also, a significant portion of those hold-time defects cannot be detected by conventional ATPG patterns for stuck-at faults or transition faults, and the top-off patterns of the defect-based hold-time faults versus stuck-at fault patterns can achieve a 19.23% coverage increase with only 0.2% pattern count overhead. The defect-based hold-time faults extracted by our framework are outputted in the UDFM format and can immediately be used for test generation with a commercial ATPG tool.

When testing scan flip-flops (SFFs), chain test is first applied to ensure the functionality of scan chains and to detect the majority of stuck-at (SA) and transition delay (TD) faults along scan paths. However, there still exist some defects inside scan cells that cannot be effectively detected by chain test or conventional SA and TD patterns. This paper presents five cell-aware (CA) fault models to explicitly target the defects inside scan flip-flops. The proposed static shift (SS) and dynamic shift (DS) faults identify the defects detectable by chain test. For the defects escaping chain test, static single-capture (SSC) faults target the defects detectable when SFFs are in one-cycle capture mode, while static double-capture (SDC) and dynamic double-capture (DDC) faults target those detectable when SFFs are in two-cycle capture mode. The identified CA faults of SFFs are output in a format compatible with a commercial ATPG tool for pattern generation. Experimental results on large IWLS05 benchmarks demonstrate that our proposed faults cannot be fully covered by conventional SA and TD patterns and hence require dedicated test patterns to detect.

In order to reduce defect parts per million, cell-aware (CA) methodology was proposed to cover various types of intracell defects. In this article, we present a novel methodology for generating 2-time-frame (2tf) CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault: 1) on a cell instance basis and 2) based on per-instance timing criticality (according to timing slack). By comparing the derived extra delay against the timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. We also propose a test quality metric, timing slack defect coverage (TSDC), to measure the effectiveness of automatic test pattern generation (ATPG) tests in terms of the ability to detect small-delay TS defects along long paths. Experimental results on a set of 22-nm industrial designs demonstrate that, due to more realistic fault identification, the number of identified small-delay faults can be reduced by 56.8%. With the slack-based ATPG for testing small-delay faults along long paths, TS can reduce the number of test patterns by 33.1% while achieving 0.49% higher TSDC, compared with the results of prior 2tf CA methodology.

A defect-based bridge fault represents the faulty behavior of an interconnect short defect obtained by SPICE simulating the two shorted cells with the short defect injected. In this article, we have developed a framework to automatically extract defect-based bridge faults and utilize commercial automatic test pattern generation (ATPG) to generate corresponding test patterns for a given design. A defect-based bridge fault model can not only describe the faulty behavior of a short defect precisely but also result in collapsible faults at one shorted cell pair. As a result, using a defect-based bridge fault model for ATPG can lead to a significantly smaller bridge-fault test set when compared with a conventional four-way dominance bridge fault model, where four noncollapsible faults at one shorted cell pair are considered for ATPG. In addition, some short defects can only be detected by the test set for defect-based bridge faults but not by the test set for four-way dominance bridge faults with more test patterns. The runtime required for extracting 1-time-frame (1tf) defect-based bridge faults has been proven acceptable on industrial designs and some techniques were also proposed to speed up the runtime for extracting 2tf defect-based bridge faults. All experiments in this article are conducted based on industrial designs.

In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.

This paper introduces a novel fault model, called the dual-cell-aware (DCA) fault model, which targets the short defects locating between two adjacent standard cells placed in the layout. A layout-based methodology is also presented to automatically extract valid DCA faults from targeted designs and cell libraries. The identified DCA faults are outputted in a format that can be applied to a commercial ATPG tool for test generation. The result of ATPG and fault simulation based on industrial designs have demonstrated that the DCA faults cannot be fully covered by the tests of conventional fault models including stuck-at, transition, bridge and cell-aware faults and hence require their own designated tests to detect.