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Ed Preisler

dblp:200/7217 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 56% Electronic design automation · 44%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits
0.312017
SiGe HBT Technology: Future Trends and TCAD-Based Roadmap · Proc. IEEE 2017
Electronic design automation
technology computer-aided design
0.312017
SiGe HBT Technology: Future Trends and TCAD-Based Roadmap · Proc. IEEE 2017
Integrated circuit design › semiconductor device modeling
compact modeling
0.112017
SiGe HBT Technology: Future Trends and TCAD-Based Roadmap · Proc. IEEE 2017

Methods — techniques the papers use, named apart from their topics

compact modeling · 0.3TCAD simulation · 0.3
YearPublicationVenuePosition
2017 SiGe HBT Technology: Future Trends and TCAD-Based Roadmap
abstract
A technology roadmap for the electrical performance of high-speed silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented based on combining the results of various 1-D, 2-D, and 3-D technology computer-aided design (TCAD) simulation tools with geometry scalable compact modeling. The latter, including all known parasitic effects, enables the accurate determination of the figures of merit for both devices and selected benchmark circuits. The presented roadmap defines five major technology nodes with the maximum oscillation frequency of a typical high-frequency device structure as the main device design target under the constraints of various other parameters for generating the doping profiles and for defining the lateral scaling factors. An extensive and consistent set of technology and electrical parameters is provided along with the obtained scaling rules. The expected fabrication-related challenges and possible solutions for achieving the predicted performance are being discussed. It is hoped that the presented roadmap will be useful not only for foundries and equipment manufacturers but also for circuit and system designers enabling better predictions of the capability of SiGe-BiCMOS process technology for new millimeter-wave (mm-wave) and terahertz (THz) applications.
Michael Schröter, Tommy Rosenbaum, Pascal Chevalier 0002, Bernd Heinemann, Sorin P. Voinigescu, Ed Preisler, Josef Bock, Anindya Mukherjee
Proc. IEEE6