Strong Physical Unclonable Functions (PUFs) are critical for lightweight authentication in the Internet of Things (IoT). However, traditional Strong PUF designs are susceptible to advanced Machine Learning (ML) modeling attacks. In this article, we propose a novel modeling-attack-resilient Strong PUF architecture that transforms the challenge-response mapping from a statically approximable function into a mathematically rigorous Keyed Pseudo-Random Function (Keyed-PRF). The proposed architecture features two core innovations: a Sponge-Based Configuration Mechanism (SCM) that utilizes reliable Weak PUFs to dynamically configure the feedback polynomial of a Linear Feedback Shift Register (LFSR), effectively creating a device-specific secret key; and a Response-Modulated State Evolution Mechanism (RM-SEM), where the instantaneous physical responses of the underlying Arbiter PUF determine the evolution step size of the LFSR. This creates a deep temporal feedback loop that transforms the system into a Hidden Markov Model (HMM), blocking gradient-based learning strategies. We also introduce a reliability screening strategy based on a strict bit-error-rate threshold to ensure stability. Experimental results on Xilinx Artix-7 FPGAs demonstrate that the proposed PUF maintains a prediction accuracy of approximately 50% against four mainstream modeling attacks even with 1 million training Challenge-Response Pairs (CRPs). Furthermore, the design exhibits excellent uniformity, uniqueness, and reliability, achieving these security properties with minimal hardware overhead.

In IoT devices, True Random Number Generators (TRNGs) play an increasingly important role, and advanced TRNGs must possess high throughput, low resource overhead, and high stability. In this article, we propose a fine-grained entropy extraction circuit based on Self-Timed Ring (STR), which can change the entropy extraction capability by varying the stages of STRs to extract randomness from different entropy sources. Importantly, the throughput of the proposed TRNG can be automatically adjusted according to the frequency of the entropy source, adapting to user requirements. The proposed TRNG is validated on Xilinx Spartan-6, Xilinx Artix-7, and Xilinx Virtex-6 FPGA development boards. It utilizes a three-stage Ring Oscillator (RO) and a five-stage RO for entropy extraction, requiring only 53 LUTs, 32 DFFs, and 62 registers. The generated random numbers of the TRNG, without any post-processing, achieve excellent results in NIST SP 800-22, NIST SP 800-90B, robustness test, universality test, AIS-31, and TEST U01, demonstrating a throughput of 280 Mbps.

In nanoscale CMOS technology, harsh radiations in the environment can now easily cause soft errors, e.g., single-event transients (SETs) and triple node upsets (TNUs), severely affecting the reliability of space applications. In this article, TNUs tolerant and SET-pulses filtered latch (TUTPFL) with low power is proposed, which comprises from four input-stage C-elements (CEs), four inverters, and three output-stage CEs. The CEs’ delay differential enables the TUTPFL latch to effectively filter SET-pulse, while the CEs’ multilevel error-interception property enables the TUTPFL latch to tolerate any possible TNU. The results of HSPICE-based simulations and FPGA-based emulations demonstrate the TNU tolerance and SET filterability of the TUTPFL latch. Meanwhile, compared to the alternative radiation-hardened latches, the TUTPFL latch reduces power dissipation by roughly 20.43% on average.

True random number generator (TRNG), essential component in cryptographic equipment, which can generate unpredictable and irreproducible key string has an important effect on information encryption. In this work, a novel low-cost, high-efficiency true random number generator based on the ring oscillator is implemented on FPGAs. Forming a tapped delay line by utilizing the fast carry logic on FPGA, we have improved the efficiency of the entropy extraction from the jitter of single transition event rather than multiple jitter accumulation like most RO-based TRNGs. In order to achieve low cost and high throughput, the delay of the ring oscillator has been optimized by deeply studying LUT structure and routing resources. The proposed architecture has been validated on Xilinx Virtex-6 FPGA, which obtains a high throughput of about 100 Mbps while occupying just 25 slices and provides robustness across a wide range of temperature (0 °C ~ 80 °C), voltage (0.9 V ~ 1.1 V) and process variation (multiple chips). And the generated random bitstreams have passed all tests in the NIST statistical test suite.

This paper describes a novel all-digital true rand-om number generator (TRNG) in SRAM-based field programable gate arrays (FPGAs), which utilizes vernier technique to high precisely quantize random edge jitter caused by thermal noise in order for on-die entropy extraction. The TRNG is implemented in three ML605 platforms and experimental result shows that the TRNG presents a high quality of randomness (passing all NIST random tests with high p-values), a high throughput of 127 Mbps, and a good tolerance to bias phenolmenon induced by process, voltage, and temperature (PVT) variations.

Physical Unclonable Functions (PUFs) promise cheap, efficient, and secure identification and authentication of devices, especially in FPGAs, which have been widely used. Various PUF implementation techniques have been proposed to translate chip-specific variations into a unique chip ID. It is difficult to guarantee the stability of the chip ID generation due to the complex operating environment. To solve this problem, in this paper, the Programmable Delay Lines (PDLs) was utilized to configure the ring oscillator to improve the stability of ID gener-ation. Compared with the original RO PUF, the proposed structure does not add extra overhead, but instead saves resources due to the compact layout. Experimental results demonstrate that the chip ID generated by our configurable ring oscillator (RO) PUFs is random (passing the NIST randomness test), and multiple measurements under a wide range of operating environments show that the proposed PUF is highly reliable (the bit flip rate is reduced from approximately 1.0% to 0 at nominal temperature and voltage conditions).

This brief presents a double-node-upset-resilient latch (DNURL) design in 22-nm CMOS technology. The latch comprises three interlocked single-node-upset-resilient cells and each of the cells mainly consists of three mutually feeding back Muller C-elements. Simulation results demonstrate the double-node upset resilience and a 73.0% delay-power-area product saving on average compared with the up-to-date DNURL designs.