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André Lopes

dblp:200/8202 · DBLP profile ↗
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3ranked-venue papers
2as first author
2since 2021 · last 2026
0009-0002-8039-9033ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 40% Memory systems · 38% Processor architecture and microarchitecture · 22%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
processing-in-memory
1.822026
Accelerating Transactional Execution via Processing-In-Memory · EuroSys 2026
PIM-STM: Software Transactional Memory for Processing-In-Memory Systems · ASPLOS (2) 2024
Parallel and multicore computing
transactional memory
1.122026
PIM-STM: Software Transactional Memory for Processing-In-Memory Systems · ASPLOS (2) 2024
Accelerating Transactional Execution via Processing-In-Memory · EuroSys 2026
Processor architecture and microarchitecture
transactional execution
1.012026
Accelerating Transactional Execution via Processing-In-Memory · EuroSys 2026
Parallel and multicore computing › transactional memory
software transactional memory
0.812024
PIM-STM: Software Transactional Memory for Processing-In-Memory Systems · ASPLOS (2) 2024

Methods — techniques the papers use, named apart from their topics

processing-in-memory · 1.0
YearPublicationVenuePosition
2026 Accelerating Transactional Execution via Processing-In-Memory
André Lopes, Daniel Castro 0004, Paolo Romano 0002
EuroSys1
2024 PIM-STM: Software Transactional Memory for Processing-In-Memory Systems
abstract
Processing-In-Memory (PIM) is a novel approach that augments existing DRAM memory chips with lightweight logic. By allowing to offload computations to the PIM system, this architecture allows for circumventing the data-bottleneck problem that affects many modern workloads.
André Lopes, Daniel Castro 0004, Paolo Romano 0002
ASPLOS (2)1
2017 A data-driven approach to help understanding the preferences of public transport users
abstract
The maintenance of the quality of the public transport service in big cities requires constant monitoring, which may become an expensive and time-consuming practice. The perception of quality, from the users point of view is an important aspect of quality monitoring. In this sense, we proposed a methodology based on big data analysis and visualization, which allows for the structuring of estimates and assumptions of where and who seems to be having unsatisfactory experiences while making use of the public transportation in metropolitan areas. Moreover, it provides support in setting up a plan for on-site quality surveys. The proposed methodology increases the likelihood that, with the on-site visits, the interviewer finds users who suffer inconveniences, which influence their behavior. Simulation comparison and a small-scale pilot survey helped validate the proposed method.
Vasco Furtado, Elizabeth Furtado, Carlos Caminha, André Lopes, Victor Dantas, Caio Ponte, Sofia Cavalcante
IEEE BigData4