This paper investigates the side-channel resistance of the ChaCha20 stream cipher on 8-bit and 32-bit microcontrollers. Using the low-cost ChipWhisperer platform, we demonstrate full keystream recovery under nonce reuse via Correlation Power Analysis (CPA). For proper nonce usage, we propose a novel two-phase CPA strategy that successfully recovers key bytes in the first column of the cipher’s internal state by exploiting second-round leakage. While full key recovery remains out of reach, the results confirm exploitable leakage and highlight practical risks in ChaCha20 implementations on embedded systems.

This paper introduces a novel side-channel attack scheme targeting FPGA implementations of the SipHash cipher, a cryptographic hash function commonly used for message authentication. At the time of writing, we were unaware of any side-channel attack on hardware implementation of the SipHash. A leakage function was built that is able to compute part of the internal state after 1 round based on just a few bits of the key. Our approach is based on progressively eliminating incorrect subkeys in iterations, while adding new bits of the key we attack, rather than trying to extract the subkey directly. The total amount of key hypotheses does not exceed a limit when it becomes unfeasible to compute. In the end, all 128 bits of the SipHash key are retrieved solely from the Hamming distance of the initial state and the state after first round.

This work presents an experimental evaluation of influence of compiler optimization flags on side-channel information leakage. Sip Hash was used as a reference algorithm an ARX - based pseudorandom function optimized for short inputs. ChipWhisperer CW308 with various targets was used for the evaluation using guessing entropy of CPA and Welch's t-test. The main contribution of this paper is analysis of impact of each flag and its suitability for implementations minimizing side-channel leakage.

SipHash is ARX-based pseudorandom function optimized for short inputs. It was developed as a hash table lookup function, but it is also used for MAC generation. At the time of writing, there was no side-channel attack on SipHash known to us. This work is about application of CPA attack on SipHash. Attack was performed on ChipWhisperer CW308 UFO Board with STM32F0 target. Approximately 800 power traces were needed for succesful attack. Leakage information from XOR was used to attack cipher key. The main contribution of this work is power model of binary addition including carry propagation.

Masking is a powerful instrument for protecting cryptographic devices against side-channel analysis. Multiple masking schemes were introduced providing provable security against attacks of arbitrary order even in the presence of glitches. When a device is a part of some safety-critical system, it needs to meet dependability requirements; therefore, it should be protected against spontaneously occurring faults. Existing commonly used fault-tolerance architectures involve high area overhead as so as the masking schemes do. In this paper, we propose architectures meeting dependability properties of simple modular-redundancy schemes and SCA resistance of masking schemes, but decreasing the area overhead utilizing the randomness involved in the masking schemes.We compare our Masked Duplex architecture with Triple Modular Redundancy. While using one less redundant module, our architecture saves around 20% of the area in comparison with TMR in the case of Threshold Implementation of PRESENT cipher, promising more savings for more complex cryptographic schemes.

This paper describes the technique of Dummy Rounds as a countermeasure against DPA in hardware implementation of round-based ciphers. Its principle is inspired by several well-known countermeasures used in hardware as Hiding and Dynamic Reconfiguration as well as countermeasures used in software implementations as Dummy cycles, Random order execution or Hiding in time. Being inspired by countermeasures based on dynamic reconfiguration, this method combines hiding of power consumption with hiding in time. In this work we also discuss the amount of randomness available for the control of the computation.

Correlation power analysis (CPA) is one of the most common side channel attacks today, posing a threat to many modern ciphers, including AES. The simplest method to extract the correct key guess is selecting the guess with the maximum Pearson correlation coefficient. We propose another distinguisher based on a significant change in the correlation trace rather than on the absolute value of the coefficient. Our approach performs better than the standard CPA, especially in the noisy environment.

Differential power analysis (DPA) is one of the most common side channel attacks. To perform this attack we need to calculate a large amount of correlation coefficients. This amount is even higher when attacking FPGAs or ASICs, for higher order attacks and especially for attacking DPA protected devices. This article explains different approaches to the calculation of correlations, describes our implementation of these approaches and presents a detailed comparison considering their performance and their properties for a practical usage.

As the security is becoming more and more important these days, we still should not forget about reliability. When designing a cryptographic device for some mission-critical or another reliability demanding system, we need to make the device not only attack-resistant, but also fault-tolerant. There are many common fault-tolerant digital design techniques, however, it is questionable, how these techniques affect the attack-resistance. Do they make the device more vulnerable e.g. to side-channel attacks?In our work we focused on finding the answer to this question. We experimentally evaluated the influence of information redundancy, space redundancy and time redundancy techniques on resistance against power analysis attack. In this paper we present our observations.