This work describes the hardware implementation of a cryptographic accelerators suite, named Crypto-Tile, in the framework of the European Processor Initiative (EPI) project. The EPI project traced the roadmap to develop the first family of low-power processors with the design fully made in Europe, for Big Data, supercomputers and automotive. Each of the coprocessors of Crypto-Tile is dedicated to a specific family of cryptographic algorithms, offering functions for symmetric and public-key cryptography, computation of digests, generation of random numbers, and Post-Quantum cryptography. The performances of each coprocessor outperform other available solutions, offering innovative hardware-native services, such as key management, clock randomisation and access privilege mechanisms. The system has been synthesised on a 7 nm standard-cell technology, being the first Cryptoprocessor to be characterised in such an advanced silicon technology. The post-synthesis netlist has been employed to assess the resistance of Crypto-Tile to power analysis side-channel attacks. Finally, a demoboard has been implemented, integrating a RISC-V softcore processor and the Crypto-Tile module, and drivers for hardware abstraction layer, bare-metal applications and drivers for Linux kernel in C language have been developed. Finally, we exploited them to compare in terms of execution speed the hardware-accelerated algorithms against software-only solutions.

Artificial intelligence (AI) is becoming increasingly relevant for space applications, reducing reliance on high-bandwidth downlinks. Its use, however, has primarily been demonstrated in low Earth orbit (LEO) using commercial off-the-shelf (COTS) components. Extending its use to deep-space and long-duration missions requires computing platforms capable of operating in harsh radiation environments without incurring prohibitive costs. This is particularly important for systems implemented on field-programmable gate arrays (FPGAs), which are widely used in space applications due to their scalability and support for various radiation-hardening profiles. This flexibility makes them preferable to application-specific integrated circuits, whose low production volumes often do not justify their use in space systems. This article details our efforts to develop a novel system-on-chip (SoC) featuring GPU@SAT, a soft graphic processing unit IP provided by IngeniArs S.r.l., with a focus on enhancing its robustness when implemented on the Xilinx radiation-tolerant XQRKU060 FPGA. This approach leverages FPGA reconfigurability and radiation tolerance alongside the high-performance capabilities of graphic processing units (GPUs), unlocking significant potential for accelerating compute-intensive tasks in edge-space applications. Building on this foundation, we employ a classification-based methodology to improve the fault tolerance of GPU@SAT, analyzing trade-offs on performance, power, and area. Additional IP cores, such as a watchdog timer (WDT), a dual RISC-V lockstep with rollback, and the Xilinx Soft Error Mitigation IP, are employed to further improve the SoC robustness. Fault injection on an FPGA prototype targeting essential configuration bits validates the approach, showing a$15.4\times $improvement in mean injections before failure over the baseline architecture, with only a$1.2\times $increase in hardware complexity.

The rapid development of Artificial Intelligence (AI) algorithms has created a need for a resource-optimised hardware accelerator. Among various platforms, Coarse-Grained Reconfigurable Array (CGRA) have gained importance as on-edge accelerators. They comprise of heterogeneous Processing Element (PE) matrix, which allows for high flexibility and parallelisation of calculations. They are mainly used for speeding up Data Flow Graph (DFG) execution. We aim to provide a general purpose, highly parameterised, and flexible architecture for AI on-edge data crunching. We propose a CGRA with a vector extension which allows for dynamically adjustable precision of calculation while maintaining a desired performance-power-area optimisation. It targets 4 bits integer (INT4) and 8 bits integer (INT8) quantization for fast and efficient Neural Network (NN) processing. In this paper, we examined hardware costs required to support the vector extension functionality. We synthesised the design on the 40nm Standard-Cell technology from TSMC. The obtained results show that the proposed extension attains on average 28.2% decrease in power consumption and 21.6% decrease in area compared to a reference design of the same computation power.

Modern computing platforms exploiting Coarse-Grained Reconfigurable Array architectures depend highly on the efficiency with which data are handled inside the architecture. Moving data is critical in computing-intensive systems to maximize energy efficiency and reduce latency. Access to the main memory is the most costly operation; therefore, the data retrieved must be kept near the processing elements of the architecture as long as possible to reduce data transfers. Modern algorithms involve very different access patterns to the main memory, requiring high versatility for Direct Memory Access (DMA) mechanisms. This work presents the SmartDMA architecture, a RISC-V-based programmable DMA controller specifically designed to perform adaptable memory access patterns and implement proper data reuse policies in CGRA-based systems. It comprises a set of Data Mover Engines (DMEs) that implement configurable 1D, 2D, and 3D data movements. Using a custom RISC-VISA extension and a programmable event network, the application-specific firmware loaded on the SmartDMA can schedule DMA commands among all DMEs, ensuring that they are always busy with data transactions. We show a typical use case that takes advantage of CGRA-based processing and highlights the functionality of the SmartDMA. We synthesized the SmartDMA on TSMC 40nm low-power standard-cell technology at 350 MHz for three architectural configurations, increasing the number of DMEs, with a maximum memory throughput of 5.6 GB/s: small, medium, and large. The small configuration occupies 46.2k um2 of cell area and consumes 8.64 mW. The medium occupies 117k um2 and consumes 23.1 mW. The large one occupies 243k um2 and consumes 42.7 mW.

This article presents a cryptographic hardware (HW) accelerator supporting multiple advanced encryption standard (AES)-based block cipher modes, including the more advanced cipher-based MAC (CMAC), counter with CBC-MAC (CCM), Galois counter mode (GCM), and XOR-encrypt-XOR-based tweaked-codebook mode with ciphertext stealing (XTS) modes. The proposed design implements advanced and innovative features in HW, such as AES key secure management, on-chip clock randomization, and access privilege mechanisms. The system has been tested in a RISC-V-based system-on-chip (SoC), specifically designed for this purpose, on an Ultrascale + Xilinx FPGA, analyzing resource and power consumption, together with system performances. The cryptoprocessor has been then synthesized on a 7-nm CMOS standard-cells technology; performances, complexity, and power consumption information are analyzed and compared with the state of the art. The proposed cryptoprocessor is ready to be embedded within the innovative European Processor Initiative (EPI) chip.

U-PHOS (Upgraded PHP Only for Space) is a project developed by a team of students from the University of Pisa with the goal to analyze and characterize the behavior of a Pulsating Heat Pipe (PHP), one of the most attractive two phases passive systems for thermal management in space applications. The PHP consists of a sealed serpentine capillary tube filled with a working fluid. The heat is efficiently transported by means of the combined action of phase change and capillary forces, so no extra equipment is required. The project aims at investigating the thermal response of such a device under a milli-gravity condition, in order to assess its effectiveness in space conditions. U-PHOS is one of the selected experiment of the REXUS/BEXUS programme, which allows European university students to carry out scientific and technical experiments on research rockets and balloons, thanks to a bilateral agency agreement between the German Aerospace Centre (DLR) and the Swedish National Space Board (SNSB) in collaboration with ESA. 19 students from the University of Pisa, with different backgrounds, compose the U-PHOS team. Students had the chance to completely design, build and test the experiment, which will flight up to space in March 2017. This paper intends to describe the work done by the students, their organization and how this experience empowered their careers, from both an academic and professional point of view.