Demo Data from EDBT 2026 / reviewers in the wild / expert
Sree Ranjani Rajendran
dblp:201/3683
· DBLP profile ↗
2ranked-venue papers
2as first author
2since 2021 · last 2024
0000-0002-7884-4049ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 77% Processor architecture and microarchitecture · 23% | |
| Network and information security
1 paper |
Hardware security and side channels · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
hardware vulnerabilities |
0.8 | 1 | 2024 | Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software · IEEE Trans. Inf. Forensics Secur. 2024 |
Electronic design automation › hardware verification and test
formal verification |
0.8 | 1 | 2024 | Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software · IEEE Trans. Inf. Forensics Secur. 2024 |
Electronic design automation › hardware verification and test
hardware verification |
0.8 | 1 | 2024 | Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software · IEEE Trans. Inf. Forensics Secur. 2024 |
Processor architecture and microarchitecture
instruction set architecture |
0.2 | 1 | 2024 | Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software · IEEE Trans. Inf. Forensics Secur. 2024 |
Processor architecture and microarchitecture › instruction set architecture
RISC-V |
0.2 | 1 | 2024 | Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software · IEEE Trans. Inf. Forensics Secur. 2024 |
Methods — techniques the papers use, named apart from their topics
threat modeling · 1.5counterexample generation · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath SoftwareabstractDue to the increasing size and complexity of system-on-chips (SoCs), new threats and vulnerabilities are emerging, mainly related to flaws at the system level. Due to the lack of decisive security requirements and properties from the perspective of the SoC designer, the system-level verification process, whose violation may lead to exploiting a hardware vulnerability, is not studied comprehensively. To enable more comprehensive verification of system-level properties, this paper presents a framework known asHUnTer(Hardware Underath Trigger) for identifying sets of instructions (sequences) at the processor unit (PU) that reveal the underlying hardware vulnerabilities. HUnTer automates (i) threat modeling, (ii) threat-based formal verification, (iii) generating counterexamples, and (iv) generating snippet code to exploit the vulnerability. Furthermore, the HUnTer framework defines a unique security coverage metric (HUnT_Coverage) to measure the performance and effectiveness of vulnerability exploits. To demonstrate the high effectiveness of the proposed framework, we conduct a wide variety of case studies using the HUnTer framework on RISC-V-based open-source SoC architecture and attains the security coverage of 86% as an average for 11 benchmarks of the Trust-Hub database. Sree Ranjani Rajendran, Nusrat Farzana, Shams Tarek, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor |
IEEE Trans. Inf. Forensics Secur. | 1 |
| 2023 | HUnTer: Hardware Underneath Trigger for Exploiting SoC-level VulnerabilitiesabstractSystems-on-chip (SoCs) have become increasingly large and complex, resulting in new threats and vulnerabilities, mainly related to system-level flaws. However, the system-level verification process, whose violation may lead to exploiting a hardware vulnerability, is not studied comprehensively due to the lack of decisive (security) requirements and properties from the SoC designer's perspective. To enable a more comprehensive verification for system-level properties, this paper presents HUnTer (Hardware Underneath Trigger), a framework for identifying sets (sequences) of instructions at the processor unit (PU) that unveils the underneath hardware vulnerabilities. The HUnTer framework automates (i) threat modeling, (ii) threat-based formal verification, (iii) generation of counterexamples, and (iv) generation of snippet code for exploiting the vulnerability. The HUnTer framework also defines a security coverage metric (HUnT_Coverage) to measure the performance and efficacy of the proposed approach. Using the HUnTer framework on a RISC-V-based open-source SoC architecture, we conduct a wide variety of case studies of Trust-HUB vulnerabilities to demonstrate the high effectiveness of the proposed framework. Sree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor |
DATE | 1 |