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Noah Chesnut

dblp:201/3925 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 87% Reconfigurable computing and FPGAs · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.412019
SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks · MICRO 2019
Hardware accelerators and domain-specific architectures › machine learning accelerator › CNN accelerator
sparse CNN accelerator
0.412019
SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks · MICRO 2019
Reconfigurable computing and FPGAs › FPGA accelerator
FPGA accelerator implementation
0.112019
SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks · MICRO 2019

Methods — techniques the papers use, named apart from their topics

inner join of sparse vectors · 0.4greedy balancing · 0.4
YearPublicationVenuePosition
2019 SparTen: A Sparse Tensor Accelerator for Convolutional Neural Networks
abstract
Convolutional neural networks (CNNs) are emerging as powerful tools for image processing. Recent machine learning work has reduced CNNs' compute and data volumes by exploiting the naturally-occurring and actively-transformed zeros in the feature maps and filters. While previous semi-sparse architectures exploit one-sided sparsity either in the feature maps or the filters, but not both, a recent fully-sparse architecture, called Sparse CNN (SCNN), exploits two-sided sparsity to improve performance and energy over dense architectures. However, sparse vector-vector dot product, a key primitive in sparse CNNs, would be inefficient using the representation adopted by SCNN. The dot product requires finding and accessing non-zero elements in matching positions in the two sparse vectors -- an inner join using the position as the key with a single value field. SCNN avoids the inner join by performing a Cartesian product capturing the relevant multiplications. However, SCNN's approach incurs several considerable overheads and is not applicable to non-unit-stride convolutions. Further, exploiting reuse in sparse CNNs fundamentally causes systematic load imbalance not addressed by SCNN. We propose SparTen which achieves efficient inner join by providing support for native two-sided sparse execution and memory storage. To tackle load imbalance, SparTen employs a software scheme, called greedy balancing, which groups filters by density via two variants, a software-only one which uses whole-filter density and a software-hardware hybrid which uses finer-grain density. Our simulations show that, on average, SparTen performs 4.7x, 1.8x, and 3x better than a dense architecture, one-sided sparse architecture, and SCNN, respectively. An FPGA implementation shows that SparTen performs 4.3x and 1.9x better than a dense architecture and a one-sided sparse architecture, respectively.
Ashish Gondimalla, Noah Chesnut, Mithuna Thottethodi, T. N. Vijaykumar
MICRO2