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Hyun Ryong Lee

dblp:201/4805 · DBLP profile ↗
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4ranked-venue papers
2as first author
2since 2021 · last 2024
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
4 papers
Performance modeling and evaluation · 39% Parallel and multicore computing · 26% Hardware accelerators and domain-specific architectures · 13%

Topics — the 12 heaviest of 14, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
processing-in-memory
0.812024
Terminus: A Programmable Accelerator for Read and Update Operations on Sparse Data Structures · MICRO 2024
Hardware accelerators and domain-specific architectures › accelerator architecture
programmable accelerator
0.812024
Terminus: A Programmable Accelerator for Read and Update Operations on Sparse Data Structures · MICRO 2024
Parallel and multicore computing
speculative parallelization
0.622018
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism · MICRO 2018
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism · ISCA 2017
Performance modeling and evaluation
benchmarking
0.612022
Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets · MICRO 2022
Performance modeling and evaluation › profiling
microarchitectural profiling
0.612022
Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets · MICRO 2022
Performance modeling and evaluation › benchmarking › benchmark design
synthetic benchmark generation
0.612022
Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets · MICRO 2022
Performance modeling and evaluation
workload characterization
0.612022
Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets · MICRO 2022
Parallel and multicore computing › transactional memory
hardware transactional memory
0.312018
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism · MICRO 2018
Parallel and multicore computing
transactional memory
0.312018
Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism · MICRO 2018
Processor architecture and microarchitecture
execution model
0.312017
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism · ISCA 2017
Parallel and multicore computing
parallel programming models
0.312017
Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism · ISCA 2017
Distributed systems
concurrency control
0.212024
Terminus: A Programmable Accelerator for Read and Update Operations on Sparse Data Structures · MICRO 2024

Methods — techniques the papers use, named apart from their topics

dataflow acceleration · 0.8address-range concurrency control · 0.8profile-guided dataset synthesis · 0.6task-based execution model · 0.3software-managed speculative actions · 0.3
YearPublicationVenuePosition
2024 Terminus: A Programmable Accelerator for Read and Update Operations on Sparse Data Structures
abstract
Sparse data structures like hash tables, trees, or compressed tensors are ubiquitous, but operations on these structures are expensive and inefficient on current systems. Prior work has proposed hardware acceleration for these operations, but these techniques have two key shortcomings: they limit the types of data structures they support, and they focus on reads but do not support fine-grained updates to these structures. We present Terminus, a programmable accelerator for read and update operations on sparse data structures. Terminus extends each general-purpose core with a programmable dataflow engine capable of accelerating a wide range of structures and operations. Terminus engines are flexible yet simple, as they focus on common operations and defer rare, complex ones to cores. Terminus features a simple concurrency control mechanism based on address ranges that enables safe updates while preserving parallelism. We evaluate Terminus on serial and parallel benchmarks on a wide range of sparse data structures. Terminus improves performance by gmean$7.4\times$over a CPU baseline, showing that Terminus can accelerate fine-grained reads and writes that were previously not possible in prior accelerators for sparse structures.
Hyun Ryong Lee, Daniel Sánchez 0003
MICRO1
2022 Datamime: Generating Representative Benchmarks by Automatically Synthesizing Datasets
abstract
Benchmarks that closely match the behavior of production workloads are crucial to design and provision computer systems. However, current approaches fall short: First, open-source benchmarks use public datasets that cause different behavior from production workloads. Second, blackbox workload cloning techniques generate synthetic code that imitates the target workload, but the resulting program fails to capture most workload characteristics, such as microarchitectural bottlenecks or time-varying behavior.Generating code that mimics a complex application is an extremely hard problem. Instead, we propose a different and easier approach to benchmark synthesis. Our key insight is that, for many production workloads, the program is publicly available or there is a reasonably similar open-source program. In this case, generating the right dataset is sufficient to produce an accurate benchmark.Based on this observation, we present Datamime, a profile-guided approach to generate representative benchmarks for production workloads. Datamime uses the performance profiles of a target workload to generate a dataset that, when used by a benchmark program, behaves very similarly to the target workload in terms of its microarchitectural characteristics.We evaluate Datamime on several datacenter workloads. Datamime generates synthetic benchmarks that closely match the microarchitectural features of these workloads, with a mean absolute percentage error of 3.2% on IPC. Microarchitectural behavior stays close across processor types. Finally, time-varying behaviors are also replicated, making these benchmarks useful to e.g. characterize and optimize tail latency.
Hyun Ryong Lee, Daniel Sánchez 0003
MICRO1
2018 Harmonizing Speculative and Non-Speculative Execution in Architectures for Ordered Parallelism
abstract
Multicore systems should support both speculative and non-speculative parallelism. Speculative parallelism is easy to use and is crucial to scale many challenging applications, while non-speculative parallelism is more efficient and allows parallel irrevocable actions (e.g., parallel I/O). Unfortunately, prior techniques are far from this goal. Hardware transactional memory (HTM) systems support speculative (transactional) and non-speculative (non-transactional) work, but lack coordination mechanisms between the two, and are limited to unordered parallelism. Prior work has extended HTMs to avoid the limitations of speculative execution, e.g., through escape actions and open-nested transactions. But these mechanisms are incompatible with systems that exploit ordered parallelism, which parallelize a broader range of applications and are easier to use. We contribute two techniques that enable seamlessly composing and coordinating speculative and non-speculative work in the context of ordered parallelism: (i) a task-based execution model that efficiently coordinates concurrent speculative and non-speculative ordered tasks, allowing them to create tasks of either kind and to operate on shared data; and (ii) a safe way for speculative tasks to invoke software-managed speculative actions that avoid hardware version management and conflict detection. These contributions improve efficiency and enable new capabilities. Across several benchmarks, they allow the system to dynamically choose whether to execute tasks speculatively or non-speculatively, avoid needless conflicts among speculative tasks, and allow speculative tasks to safely invoke irrevocable actions.
Mark C. Jeffrey, Victor A. Ying, Suvinay Subramanian, Hyun Ryong Lee, Joel S. Emer, Daniel Sánchez 0003
MICRO4
2017 Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism
Suvinay Subramanian, Mark C. Jeffrey, Maleen Abeydeera, Hyun Ryong Lee, Victor A. Ying, Joel S. Emer, Daniel Sánchez 0003
ISCA4