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Emiliano Silvestri

dblp:201/4830 · DBLP profile ↗
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5ranked-venue papers
3as first author
1since 2021 · last 2022
0000-0002-3330-2529ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel programming runtimes
OpenMP runtime
0.612022
Effective Runtime Management of Tasks and Priorities in GNU OpenMP Applications · IEEE Trans. Computers 2022
Parallel and multicore computing
parallel programming models
0.612022
Effective Runtime Management of Tasks and Priorities in GNU OpenMP Applications · IEEE Trans. Computers 2022
Parallel and multicore computing › parallel programming runtimes
runtime systems and scheduling
0.612022
Effective Runtime Management of Tasks and Priorities in GNU OpenMP Applications · IEEE Trans. Computers 2022
Parallel and multicore computing
task scheduling
0.612022
Effective Runtime Management of Tasks and Priorities in GNU OpenMP Applications · IEEE Trans. Computers 2022

Methods — techniques the papers use, named apart from their topics

user-space library · 0.6kernel-level module · 0.6
YearPublicationVenuePosition
2022 Effective Runtime Management of Tasks and Priorities in GNU OpenMP Applications
abstract
OpenMP has become a reference standard for the design of parallel applications. This standard is evolving quickly, thus offering new opportunities to the application programmers. However, OpenMP runtime environments are often not fully aligned with the actual requirements imposed by the evolution of such a standard. Among the main lacks, we find: (a) a limited capability to effectively cope with task priorities, and (b) the inadequacy in guaranteeing core properties while processing tasks such as the so-calledwork-conservativeness—the ability of the OpenMP runtime environment to fully exploit the underlying multi-processor/multi-core machine through the avoidance of thread-blocking phases. In this article, we present the design of extensions to the GNU OpenMP (GOMP) implementation, integrated intogcc, which allow the effective management of tasks and their priorities. Our proposal is based on a user-space library—modularly combined with the one already offered byGOMP—and an external kernel-level Linux module—offering the opportunity to exploit raising hardware facilities for task/priority management. We also provide experimental results showing the effectiveness of our proposal, achieved by running either OpenMP common benchmarks or a new benchmark application (Hashtag-Text) that we explicitly devised to stress the runtime environment in relation to the above-mentioned task/priority management aspects.
Emiliano Silvestri, Alessandro Pellegrini 0001, Pierangelo di Sanzo, Francesco Quaglia
IEEE Trans. Computers1
2020 Exploiting Inter-Processor-Interrupts for Virtual-Time Coordination in Speculative Parallel Discrete Event Simulation
abstract
Reducing the waste of resource usage (e.g., CPU-cycles) when a causality error occurs in speculative parallel discrete event simulation (PDES) is still a core objective. In this article, we target this objective in the context of speculative PDES run on top of shared-memory machines. We propose an Operating System approach that is based on the exploitation of the Inter-Processor-Interrupt (IPI) facility offered by off-the-shelf hardware chipsets, which enables cross-CPU-core control of the execution flow of threads. As soon as a thread T produces a new event placed in the past virtual time of a simulation object currently run by another thread T', our IPI-based support allows T to change the execution flow of T'---with very minimal delay---so to enable the early squash of the currently processed (and no longer consistent) event. Our solution is fully transparent to the application level code, and is coupled with a lightweight heuristic-based mechanism that determines the actual goodness of killing thread T' via the IPI (rather than skipping the IPI send) depending on the expected residual execution time of the incorrect event being processed. We integrated our proposal within the speculative open-source USE (Ultimate Share Everything) PDES package, and we report experimental results obtained by running various PDES models on top of two shared-memory hardware architectures equipped with 32 and 24 (48 Hyper-threads) CPU-cores, which demonstrate the effectiveness of our proposal.
Emiliano Silvestri, Cristian Milia, Romolo Marotta, Alessandro Pellegrini 0001, Francesco Quaglia
SIGSIM-PADS1
2018 Model-Based Proactive Read-Validation in Transaction Processing Systems
abstract
Concurrency control protocols based on read-validation schemes allow transactions which are doomed to abort to still run until a subsequent validation check reveals them as invalid. These late aborts do not favor the reduction of wasted computation and can penalize performance. To counteract this problem, we present an analytical model that predicts the abort probability of transactions handled via read-validation schemes. Our goal is to determine what are the suited points-along a transaction lifetime-to carry out a validation check. This may lead to early aborting doomed transactions, thus saving CPU time. We show how to exploit the abort probability predictions returned by the model in combination with a threshold-based scheme to trigger read-validations. We also show how this approach can definitely improve performance-leading up to 14 % better turnaround-as demonstrated by some experiments carried out with a port of the TPC-C benchmark to Software Transactional Memory.
Simone Economo, Emiliano Silvestri, Pierangelo di Sanzo, Alessandro Pellegrini 0001, Francesco Quaglia
ICPADS2
2017 Preemptive Software Transactional Memory
abstract
In state-of-the-art Software Transactional Memory (STM) systems, threads carry out the execution of transactions as non-interruptible tasks. Hence, a thread can react to the injection of a higher priority transactional task and take care of its processing only at the end of the currently executed transaction. In this article we pursue a paradigm shift where the execution of an in-memory transaction is carried out as a preemptable task, so that a thread can start processing a higher priority transactional task before finalizing its current transaction. We achieve this goal in an application-transparent manner, by only relying on Operating System facilities we include in our preemptive STM architecture. With our approach we are able to re-evaluate CPU assignment across transactions along a same thread every few tens of microseconds. This is mandatory for an effective priority-aware architecture given the typically finer-grain nature of in-memory transactions compared to their counterpart in database systems. We integrated our preemptive STM architecture with the TinySTM package, and released it as open source. We also provide the results of an experimental assessment of our proposal based on running a port of the TPC-C benchmark to the STM environment.
Emiliano Silvestri, Simone Economo, Pierangelo di Sanzo, Alessandro Pellegrini 0001, Francesco Quaglia
CCGrid1
2017 Prompt application-transparent transaction revalidation in software transactional memory
abstract
Software Transactional Memory (STM) allows encapsulating shared-data accesses within transactions, executed with atomicity and isolation guarantees. The assessment of the consistency of a running transaction is performed by the STM layer at specific points of its execution, such as when a read or write access to a shared object occurs, or upon a commit attempt. However, performance and energy efficiency issues may arise when no shared-data read/write operation occurs for a while along a thread running a transaction. In this scenario, the STM layer may not regain control for a considerable amount of time, thus not being able to early detect if such transaction has become inconsistent in the meantime. To tackle this problem we present an STM architecture that, thanks to a lightweight operating system support, is able to perform a fine-grain periodic (hence prompt) revalidation of running transactions. Our proposal targets Linux and x86 systems and has been integrated with the open source TinySTM package. Experimental results with a port of the TPC-C benchmark to STM environments show the effectiveness of our solution.
Simone Economo, Emiliano Silvestri, Pierangelo di Sanzo, Alessandro Pellegrini 0001, Francesco Quaglia
NCA2