EDBT 2026 Demo / reviewers in the wild / expert
Hanna Alam
dblp:201/4859
· DBLP profile ↗
2ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0007-1020-2713ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Performance modeling and evaluation · 55% Electronic design automation · 34% Memory systems · 11% | |
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 100% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
analytical modeling |
0.9 | 1 | 2025 | Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion · ISCA 2025 |
Electronic design automation
design space exploration |
0.9 | 1 | 2025 | Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion · ISCA 2025 |
Performance modeling and evaluation › surrogate modeling
machine-learning-based performance modeling |
0.9 | 1 | 2025 | Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion · ISCA 2025 |
Electronic design automation › design space exploration
microarchitecture design space exploration |
0.9 | 1 | 2025 | Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion · ISCA 2025 |
Performance modeling and evaluation
processor performance modeling |
0.9 | 1 | 2025 | Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion · ISCA 2025 |
Memory systems › memory management › virtual memory
address translation |
0.3 | 1 | 2017 | Do-It-Yourself Virtual Memory Translation · ISCA 2017 |
Memory systems › memory management
virtual memory |
0.3 | 1 | 2017 | Do-It-Yourself Virtual Memory Translation · ISCA 2017 |
Performance modeling and evaluation › simulation › architectural simulation
cycle-accurate simulation |
0.3 | 1 | 2025 | Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML Fusion · ISCA 2025 |
Operating systems › resource management
memory management |
0.1 | 1 | 2017 | Do-It-Yourself Virtual Memory Translation · ISCA 2017 |
Methods — techniques the papers use, named apart from their topics
machine learning · 0.9analytical modeling · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | Concorde: Fast and Accurate CPU Performance Modeling with Compositional Analytical-ML FusionabstractCycle-level simulators such as gem5 are widely used in microarchitecture design, but they are prohibitively slow for large-scale design space explorations.We present Concorde, a new methodology for learning fast and accurate performance models of microarchitectures.Unlike existing simulators and learning approaches that emulate each instruction, Concorde predicts the behavior of a program based on compact performance distributions that capture the impact of different microarchitectural components.It derives these performance distributions using simple analytical models that estimate bounds on performance induced by each microarchitectural component, providing a simple yet rich representation of a program's performance characteristics across a large space of microarchitectural parameters.Experiments show that Concorde is more than five orders of magnitude faster than a reference cycle-level simulator, with about 2% average Cycles-Per-Instruction (CPI) prediction error across a range of SPEC, open-source, and proprietary benchmarks.This enables rapid design-space exploration and performance sensitivity analyses that are currently infeasible, e.g., in about an hour, we conducted a first-of-its-kind fine-grained performance attribution to different microarchitectural components across a diverse set of programs, requiring nearly 150 million CPI evaluations. Arash Nasr-Esfahany, Mohammad Alizadeh, Victor Lee, Hanna Alam, Brett W. Coon, David E. Culler, Vidushi Dadu, Martin Dixon, Henry M. Levy, Santosh Pandey 0001, Parthasarathy Ranganathan, Amir Yazdanbakhsh |
ISCA | 4 |
| 2017 | Do-It-Yourself Virtual Memory TranslationabstractIn this paper, we introduce the Do-It-Yourself virtual memory translation (DVMT) architecture as a flexible complement for current hardware-fixed translation flows. DVMT decouples the virtual-to-physical mapping process from the access permissions, giving applications freedom in choosing mapping schemes, while maintaining security within the operating system. Furthermore, DVMT is designed to support virtualized environments, as a means to collapse the costly, hardware-assisted two-dimensional translations. We describe the architecture in detail and demonstrate its effectiveness by evaluating several different DVMT schemes on a range of virtualized applications with a model based on measurements from a commercial system. We show that different DVMT configurations preserve the native performance, while achieving speedups of 1.2x to 2.0x in virtualized environments. Hanna Alam, Mattan Erez, Yoav Etsion |
ISCA | 1 |