The multi-stage charge pump in a zero-crossing-based amplifier (ZCBA) presents complex trade-offs. In this brief, we propose a generalized behavioral model for the ZCBA to quickly predict the optimal charge pump design for a ZCBA based on circuit parameters, without conducting time-consuming transistor-level simulations iteratively. This model enables us to numerically analyze in MATLAB the effects of the circuit parameters, which include the current scaling factor, number of current sources, current value, and input amplitude, on the settling performance including overshoot and settling time. The analysis results conclude that there exists an optimal number of stages that yields the fastest settling time for a given total current and load capacitance. Additionally, the settling time exhibits an asymptotic behavior with respect to the total current. To validate this behavioral model, we designed and simulated a transistor-level ZCBA in a 28-nm CMOS process, demonstrating a good agreement between the model analysis and simulation result.

Community search (CS) is an important research topic in network analysis, which aims to find a subgraph that satisfies the given conditions. A dynamic attribute heterogeneous information network (DAHIN) is a sequence of attribute heterogeneous information network (AHIN) snapshots, where each snapshot consists of multiple types of vertices as well as edges, and each vertex is associated a set of attribute keywords. CS over DAHIN faces many challenges. In this paper, we study the CS problem over DAHINs, aiming to search for cohesive subgraphs containing query vertex and simultaneously satisfying the connectivity, attribute cohesiveness and interaction stability. To this end, we propose a deep learning model with a three-level attention mechanism and the concept of interaction frequency with respect to multiple semantic relationships to measure the similarity of attributes and the stability of interactions between vertices respectively. In addition, we design three search algorithms to locate the target community by optimizing the degree of interaction stability and attribute similarity between vertices. Extensive experiments, including comparison with existing algorithms, ablation analysis, parameter sensitivity examination, and case studies, are conducted on four real-world datasets to validate the effectiveness and efficiency of the proposed model and search algorithms. The code and model of CS-DAHIN will be open source on GitHub.

This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for low-power applications. To tolerate the severe variations in the subthreshold regime, a novel dynamic bulk biasing circuit senses the NMOS/PMOS strength ratio in the background and applies feedback to equalize the strengths to maintain the circuit functionality. A rigorous analysis examines the dynamics and convergence of the proposed biasing circuit in the time- and$z$-domains. A new comparator relaxes the stringent speed-noise trade-off under the 0.2-V supply. Employing switched ac-coupling, stacked input pairs, and voltage-boosted load capacitors, the comparator achieves more than a threefold improvement in speed with little noise penalty. The DAC implements grouped capacitors with quantized sub-radix-2 scaling for redundancy and low power and achieves 10-bit matching. Details of the complete ADC design are described. The measured ADC consumes 22 nW and exhibits a peak DNL and INL of 0.45 LSB and 0.67 LSB, respectively. The measured SFDR and SNDR at Nyquist are 70.6 dB and 52.8 dB, respectivley, yielding an FoM of 12.3 fJ/conv.-step. Measurements show the dynamic bulk biasing compensates the N/P strength ratio variations to optimize the SNDR. We also show that the proposed dynamic bulk biasing successfully maintains the ADC performance over supply variations and improves the yield by nearly twofold over 20 chips.

A charge amplifier incorporates digital circuits as an alternative to the classic analog amplifier to achieve a high open-loop gain to maintain a consistent closed-loop gain over input capacitance variations. The digital-assisted charge amplifier employs a comparator, digital control logic, differential charge pump, current sources, common-mode feedback, and clock generator. A detailed analysis studies the amplifier stability and trade-off between ripple voltage and settling speed. A novel two-step reset scheme and tri-state charge pump minimize the output offset due to ripple residues. Fabricated in a 180-nm CMOS process, the digital-assisted amplifier achieves an open-loop gain of 101 dB, closed-loop gain of$15.0~\mu \text{V}$/e-, input-referred noise of 221$\text{e}^{-}$rms, and output swing of 3 V while consuming 2.19 mW. The amplifier also demonstrates the ability to amplify a dynamic input current using a custom opto-electronic test setup. The amplifier maintains a consistent closed-loop gain across parasitic input capacitance from 6 pF to 94 pF.

A detector connected to a charge amplifier adds parasitic input capacitance that alters the amplifier's gain. The detector capacitance therefore must be characterized so as to properly account for its effect. This paper presents a novel, compact technique to measure the detector capacitance by exploiting the circuit elements within the charge amplifier itself. Reconfiguring the charge amplifier with programmable switches, a capacitor divider network emerges to measure the detector capacitance without the need for any accurate timing references and complex controls. Experimental results of the proposed charge amplifier fabricated in a 180-nm CMOS technology demonstrate the ability to measure the detector capacitance to within 3% of its actual value. An actual charge measurement is also presented.