The generalized integrated interleaved (GII) codes can nest BCH sub-codewords to form more powerful BCH codewords. GII codes enable hyper-speed decoding and achieve excellent error-correction capability. They are among the best candidates for the new storage class memories (SCMs). However, SCMs require high code rate and short codeword length. In this case, the GII sub-codewords have small correction capability, and miscorrections on the sub-words lead to severe performance degradation. In previous work, higher-order nested syndromes are computed to detect and mitigate miscorrections in GII decoding. These computations cause long decoding latency, even though they can be implemented by sharing the hardware architecture for other decoding steps. This paper proposes three methods to optimize the miscorrection detection by investigating dominant error patterns leading to miscorrections. The first scheme is to skip the nested syndrome checking for cases that are less likely miscorrected. To make up for the performance loss caused by the first scheme, our second approach exploits 2-bit extended BCH codes to protect each sub-codeword. In addition, the third scheme is developed to protect all sub-codewords using extra parity bits while keeping the code rate loss negligible. Formulas are also derived to estimate the achievable performance. Applying the proposed optimizations, the average nested decoding latency is reduced by 43% for an example GII code with 3-error-correcting sub-codewords at input bit error rate 10−3, while the performance loss and complexity overheads are negligible.

Generalized integrated interleaved (GII) codes can nest BCH sub-codewords to form stronger BCH codewords. They are among the best candidates for error correction in the new storage class memories (SCMs). However, SCMs require short codeword length and low redundancy. In this case, the nested key equation solver (KES), which is a key step in GII decoding, has a small number of iterations. The initialization and/or scalar pre-computation in previous nested KES designs have large area and may take even longer time than the iterations themselves. This paper proposes an efficient nested KES design for short GII-BCH codes. The polynomial updating is decomposed into two steps to reduce the critical path without requiring scalar pre-computation. Besides, the KES is reformulated to reduce the number of clock cycles without incurring any area overhead. For an example code over $GF(2^{10})$ that protects 2560 bits with 10% redundancy, the proposed design achieves at least 25% area reduction and 37% reduction on the area-time product averaged over the nested decoding rounds compared to prior efforts.

Generalized integrated interleaved (GII) codes nest short BCH sub-codewords to form more powerful BCH codewords. They can potentially achieve hyper-speed decoding with excellent error-correction capability. In particular, short GII-BCH codes are among the best candidates for the new fast storage class memories (SCMs). Miscorrections severely degrade the performance of short GII-BCH codes. Although they were effectively mitigated in previous designs, the involved repeated Chien search and higher-order syndrome computation cause long latency. This brief proposes efficient and low-latency nested decoding schemes for short GII-BCH codes. A strategy is developed to select sub-words for further nested decoding to mitigate miscorrections by keeping track of the error locator polynomials, instead of waiting for the lengthy Chien search. Formulas are also derived to estimate the effects on the error-correcting performance. Besides, a low-complexity linear feedback shift register (LFSR) architecture is developed to accelerate the higher-order nested syndrome computation. For an example GII-BCH code targeting at SCMs, the proposed design reduces the worst-case nested decoding latency by 26% with 8.5% area overhead and negligible performance loss compared to prior methods.

The generalized integrated interleaved BCH (GII-BCH) codes are among the best error-correcting codes for next-generation terabit/s memories. The key equation solver (KES) in the nested decoding of GII codes limits the achievable clock frequency. Recently, by polynomial scalar pre-computation, the critical path of the nested KES for Reed-Solomon (RS)-based GII codes has been reduced to one multiplier. However, for GII-BCH codes, the nested KES has more complicated formulas in order to skip the odd iterations and hence prior techniques do not directly extend. This paper proposes novel reformulations of the nested BCH KES to enable scalar pre-computation. Additionally, polynomial scaling is incorporated to enable complexity reduction. As a result, the critical path of the nested BCH KES with odd iterations skipped is reduced to one multiplier. For an example GII-BCH code over GF (212), the proposed design reduces the average nested BCH KES latency to around a half with similar silicon area compared to the best prior design.

Generalized integrated interleaved (GII) codes nest Reed-Solomon (RS) or BCH sub-codewords to generate codewords belonging to stronger RS or BCH codes. Their hyper-speed decoding and good error-correction capability make them one of the best candidates for next-generation terabit/s digital storage and communications. The key equation solver (KES) in the nested decoding stage causes clock frequency bottleneck and takes a large portion of the GII decoder area. Recent architectures reduce the critical path to two multipliers and rely on the application of the slow-down technique to further reduce it to one. The slow-down technique requires two sub-codewords to be interleaved in the nested KES. However, most of the time, the nested decoding only needs to be carried out on one sub-codeword and half of the clock cycles are wasted. This paper proposes two fast nested KES algorithms, both of which have one multiplier in the critical path without applying slow-down and accordingly reduce the latency of the nested KES to almost a half. The short critical path is achieved by algorithmic reformulations that enable the pre-computation of the scalars in parallel with polynomial updating. Our second design adopts scaled versions of the polynomials to enable product term sharing so that the number of multipliers in each pair of processing elements is reduced from 8 as in the first design to 4. Novel scaling and combined scalar computations are developed to keep the critical path one multiplier. For an example GII code over$GF(2^{8})$that has 3 nested codewords, our designs achieve 49.9% reduction on the number of clock cycles needed in the nested KES compared to prior designs. Besides, our second design requires 22% less area than the first one under the same timing constraint.

Generalized integrated interleaved (GII) codes allow localized decoding of short sub-codewords. They are essential to hyper-speed data storage, communications, and continued scaling of distributed storage. Sub-codewords, which are usually Reed-Solomon (RS) or BCH codewords, are nested to generate codewords of higher correction capabilities. If the decoding of individual sub-codewords fails, the higher-order syndromes from the nested codewords are utilized to correct more errors. GII decoder design faces many challenges. The major ones include: 1) high-speed nested decoding utilizing the higher-order syndromes; 2) efficient updating of higher-order syndromes after sub-codewords are corrected; 3) computation of nested syndromes and matrix inversion for converting them to higher-order sub-codeword syndromes; and 4) efficient architectures capable of addressing the variable correction capabilities of the nested codewords. This paper proposes novel algorithmic reformulations and architectural transformations to address each bottleneck. For an example, GII code that has the same rate and length as eight un-nested (255, 223) RS codes, the proposed GII decoder achieves more than seven orders of magnitude improvement in error-correcting performance with less than 30% area overhead compared to the RS decoder. With a critical path of seven XOR gates, the proposed decoder can easily achieve more than 40 GByte/s throughput.