This paper introduces a scalable SPICE-based tool infrastructure designed to optimize analog compute-in-memory (ACIM) architectures utilizing emerging non-volatile resistive memory (eNVM) technologies. The inherent efficiency of analog eNVM crossbar arrays in performing matrix-vector multiplications significantly enhances the power, performance, and area efficiency of edge AI devices and other applications. Our framework addresses the challenges of accurately simulating ACIM architectures, which are highly susceptible to variations in process, voltage, temperature, and analog noise. The framework uses SPICE for accurate analog and mixed-signal circuit simulation. It automates the generation of SPICE-level ACIM designs for deep neural networks. Additionally, it speeds up the simulation runtime by up to 35× for large DNN models while maintaining the same SPICE-level accuracy. Moreover, it ensures simulation convergence for large netlists, facilitating SPICE simulation of large-scale eNVM crossbars that were previously impractical. We demonstrated that our framework is capable of simulating inference using netlists for MLPs with over 800,000 parameters trained on the MNIST dataset within acceptable runtime, where contemporary SPICE simulators do not even converge. We validated the simulation results in terms of inference accuracy, which shows less than a 3.8% accuracy drop compared to software-based inference results. Lastly, we demonstrated the integration of our framework with an architectural simulator, facilitating comprehensive system-level simulation.

We present a cascaded chaotic system as a hardware-efficient way of elevating the entropy in the chaotic behavior of CMOS-based chaotic maps. The chaotic performance of the proposed scheme is evaluated using the bifurcation plot, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient. The improved entropy in the chaotic region benefits many security applications and is demonstrated experimentally in a new random number generator (RNG) design based on the proposed map. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), the proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise which renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded map, significantly low area and power overhead are achieved in the RNG design and it passes three statistical tests namely, NIST, Diehard, and TestU01.

A physically unclonable and reconfigurable computing system is introduced which provides both logic locking and authentication of devices. A chaotic oscillator is required to generate the chaotic signals and can produce different Boolean functions using different tuning parameters, including a control bit, iteration number, threshold voltage, and bifurcation parameter. The aim of this article is to build a hybrid computing system with the mixed implementation of standard logic gates and reconfigurable chaos-based logic gates. The tuning parameters of the oscillator make up the secret key for logic locking. Process variation due to fabrication can be leveraged to generate unique keys for each chip. The whole computing system exhibits physical unclonable function (PUF) characteristics and can be used to generate challenge-response pairs (CRPs) for authenticating devices. We have used ISCAS'85 combinational benchmark circuits to demonstrate the results. The Hamming distance between correct and wrong outputs is calculated to ensure that 50% of the output bits are flipped when the wrong key is applied. A Boolean SAT attack has been carried out on the system and it displays exponential complexity with an increase in the total number of chaos gates and key size of each chaos gate. The hybrid system demonstrates near-ideal PUF metrics, including uniqueness, uniformity, and bit aliasing. Common machine learning attacks have been executed on the CRPs generated from the whole system and results show that the proposed chaos-based PUF is robust against modeling attacks. The hybrid system has significantly less overhead compared to traditional systems containing both logic locking and PUF circuitry.

Conventional digital logic operations have distinguishable power signatures. Side channel power analysis combined with classification algorithm can reveal unknown logic operations. Revealing the underlying operations is the main task in reverse engineering an application. In this paper, we propose an unconventional way of overcoming this vulnerability by using chaos based reconfigurable logic operations. The chaos gate used in this paper is built from a simple 3 transistor chaotic oscillator capable of generating aperiodic states starting from a suitably chosen initial condition. We propose a design methodology using chaos gate to implement different logic operations with very similar power profiles. Therefore, it becomes significantly harder to distinguish logical operations built with chaotic logic gates in contrast to the conventional static CMOS logic gates. In addition, we show a mixed implementation of bitwise logic operations using different proportions of chaos and conventional gates resulting in a significant reduction of total overhead.

Emerging nano-devices like memristors display stochastic switching behavior which poses a big uncertainty in their implementation as the next-generation CMOS alternative. However, this stochasticity provides an opportunity to design circuits for hardware security. There are several examples in literature where the stochastic switching time of memristors are used as the source of entropy to build true random number generators (TRNGs). Software-based pseudo-random numbers may not be random enough for many different applications where true random numbers are a necessity. In this work, we have analyzed traditional TRNG designs that utilize memristors' switching time and evaluated them in varying operating conditions and with process variation in mind. Specifically, we have mathematically formulated how large process variation and strong temperature and voltage dependence of memristors can degrade the performance of these TRNGs. Depending on these analyses, we also have proposed a new way of designing memristive TRNG based on difference between stochastic high resistance states of a pair of memristors. Using simple probabilistic mathematics, we have evaluated our proposed method with existing ones and shown that our proposed design is robust in unfavorable environmental conditions and in the presence of large process variation where traditional TRNG bit quality degrades rapidly.

Recent advances in resistive random access memory (RRAM) as high density, low power, and faster memory systems drive the need for devising a more lightweight integrity checking system for RRAM. In this paper, we design a new tag generation system for integrity checking of RRAM. A single read operation to a crossbar RRAM in the presence of sneak path currents can output a tag for the memory data that can be used for integrity checking. An analytical approach to model such a tag generation process is described in this paper. Security results predicted by the analytical model provide various design options leading to an optimal system from the perspective of considered security properties. The proposed design is simulated to investigate and verify the security properties of the system for a number of optimal design options predicted by the analytical model. Reliability of the proposed system is also measured for varying conditions of device parameters, operating temperatures, load resistances, and read voltage. Finally, the performance of the proposed system is compared against another existing lightweight tag generation method from the perspective of energy consumption, transistor count, and delay.