A new broadband DC-bias included model for radio frequency (RF) power transistors is presented in this paper. The proposed method utilizes the canonical section-wise piecewise linear (CSWPL) model framework in order to incorporate both frequency as well as bias information simultaneously. Detailed descriptions of the fundamental theory of the developed model are provided, along with their validation through experiments. The model is implemented in commercial software and validated using DC and RF tests with measured load-pull data from a 10-W GaN device. In contrast to standard and bias-included CSWPL models, this model can predict transistor behavior under a variety of bias voltages and frequencies using only one set of parameters, thereby significantly reducing model complexity. Additionally, the proposed model is applied to a multi-octave PA design to provide further validation. Measurements made on the realized PA are compared to simulations based on the proposed model. Validity of the extracted model is confirmed by the agreement between measurements and simulations.

This paper introduces a new method for designing power amplifiers (PAs) using a flexible, automatic approach. It employs a Gaussian process-assisted fast non-dominated sorting genetic algorithm (GP-NSGA-II) for both circuit synthesis and layout optimization. Traditional genetic algorithms are computationally intensive and have poor convergence, making them difficult to use with three-dimensional full-wave simulators. To address these issues, the authors incorporate Gaussian process regression from Bayesian optimization into NSGA-II, improving convergence and computational efficiency. The method integrates layout simulation and optimization, enabling automatic PA design with direct layout optimization. To demonstrate the method’s effectiveness, the authors design a wide-band PA and a tri-band PA using a 10-W gallium-nitride (GaN) high electron mobility transistor (HEMT). The tests show that the prototypes perform well: the wide-band PA has a power-added efficiency (PAE) of over 61% and an output power greater than 41.5 dBm in the 2-3 GHz band, while the tri-band PA achieves PAE values of over 59%, 55%, and 57% in the 0.7-1.1 GHz, 2.3-2.5 GHz, and 3.4-3.5 GHz bands, respectively, with output powers exceeding 41.2 dBm, 40.6 dBm, and 40.6 dBm.

This paper presents a broadband Gallium Arsenide (GaAs) heterojunction bipolar transistor (HBT) Doherty power amplifier (DPA) that employs a lumped compensation network (LCN) and input phase correction technique for 5G applications. A LCN is utilized with an integrated impedance inverter to enhance output power back-off (OBO) efficiency across a wide frequency range. To mitigate the overdrive issue caused by the LCN under saturation, different input phase strategies are analyzed, and an on-chip coupler-based input phase correction network is introduced to maintain a constant phase difference between the carrier and peaking paths. The DPA is implemented using a 2$\mu $m GaAs HBT process and achieves broadband operation over 3.1-4.3 GHz with a fractional bandwidth exceeding 32%, covering the 5G n77 and n78 bands. Measurement results demonstrate a saturated output power of 32.73-33.77 dBm with a saturated power-added efficiency (PAE) of 39.54%-46.51%, a small-signal gain of 22.19-25.30 dB. At 6 dB OBO, the DPA maintains a PAE of 30.84%-34.95%. When tested with a 100 MHz bandwidth 64-QAM signal with 5.6 dB PAPR, the DPA achieves an average PAE of up to 34.3% and an adjacent channel power ratio (ACPR) better than -45.2 dBc after digital predistortion (DPD), demonstrating its potential for wideband 5G terminal applications.

Artificial intelligence (AI) techniques are increasingly being used for the inverse design of microwave devices. However, several challenges, including intensive computation costs for training samples, high-dimensional data, nonuniformity, and low-quality samples in the design space, can negatively impact the final modeling performance. To alleviate these issues, a high-quality sampling inverse design scheme incorporating wavelet transform deep learning (HQS-WTDL) is proposed to achieve customized, automated microwave filter design. In the forward simulation-based sampling, particle swarm optimization (PSO) is used to tentatively select rule-defined samples. Multilabel synthetic minority over-sampling technique (MLSMOTE) is then applied to enlarge the training samples and improve their uniformity in the design space. An inverse modeling approach using neural networks to map the nonlinear relationship between a given set of S-parameters and required filter structural parameters is presented. Given that the dimension of the S-parameters is much higher than that of the structure parameters, the corresponding neural network used in this approach is deep and complex, with multiple layers and neurons. To reduce the number of input variables, the S-parameters are subjected to wavelet transformation, allowing for more efficient representation by the neural network. The proposed method is validated using a band-pass microstrip hairpin filter as an example. Results demonstrate that the proposed approach achieves better modeling effectiveness and inverse design efficiency than conventional methods. In addition, the proposed method allows for fast customization of device parameters, such as center frequencies and bandwidths with good prediction accuracy.

5G and future 6G wireless communication systems are pushing the practical limits on the modulation schemes that can be achieved in practice. These higher-level modulation schemes have further exacerbated the challenges in power amplifier (PA) design. One solution to linearly and efficiently amplify these modulation schemes that have high peak-to-average power ratios (PAPRs), is to use dual-input Outphasing PAs (OPAs). However, the output back-off (OBO) range of a conventional OPA is limited. To mitigate this issue, a new OPA based on an asymmetric architecture is proposed. This new asymmetric OPA is shown theoretically that the OBO range can be extended. To validate the proposal, an OPA is designed using two asymmetric sub-PAs and a modified Chireix combiner. The implemented OPA achieves drain efficiencies of 60.6% and 60% at saturation (44.1dBm) and at 8-dB OBO under CW excitation at 2.58 GHz, respectively. Measurement of the OPA using 20-MHz 5G NR signal with 8-dB PAPR yields an average drain efficiency of 58.3% with an adjacent channel power ratio (ACPR) below −45.1 dBc with digital pre-distortion (DPD).

This article presents a theoretical analysis and circuit design for an enhanced dual-mode reciprocal Doherty power amplifier (DM-RDPA). To achieve bandwidth enhancement, an improved combining load design strategy is proposed, providing more accurate back-off impedance across a wider target bandwidth. Additionally, a sweeping analysis method is developed to determine optimal design parameters. The enhanced combining load design space of the proposed DM-RDPA is visualized, providing an intuitive view of the appropriate impedance solution space. To validate this enhanced DM-RDPA architecture and the corresponding design analysis method, a prototype PA was designed and fabricated using commercial GaN transistors. The implemented PA achieves two different Doherty operation bands: 0.95-1.9 GHz (66.7% fractional bandwidth) in Mode I and 0.67-0.93 GHz (32.5% fractional bandwidth) in Mode II. Drain efficiency of 47.3%-62.2% and 44.7%-62.1% is obtained by the fabricated DPA at 6 dB back-off in Mode I and Mode II, respectively. When driven by a 20 MHz modulated signal with 8 dB peak to average power ratio (PAPR), the fabricated DPA presents higher than 42% average efficiency in both Mode I and Mode II.

The article proposes a modified series compensation (MSC) outphasing power amplifier (OPA) that maximizes saturation output power and extends power back-off range. The proposed OPA enables achieving output power back-off (OBO) compensation without affecting the saturation matching. Then, the circuit structure is simplified by introducing a post-matching circuit to integrate the combiner and the reactive compensation network (RCN). Moreover, a simplified dual-impedance matching network (DIMN) is placed between each transistor and the output combiner, leading to increased OBO range with improved efficiency. This technique not only takes into consideration the influence of parasitic parameters but also match the required impedance at both saturation and OBO points, simultaneously. The above design idea is successfully verified by using the gallium nitride (GaN) high-electron-mobility transistor (HEMT) to develop an OPA circuit operating at 2.6 GHz, providing 45.2 dBm of peak output power. At the 12-dB output back-off point, the drain efficiency reaches 61.5%. In addition, the prototype achieves values of the adjacent channel leakage ratio (ACLR) equal to -48.17 dBc and 47.74 dBc for LTE modulated signal with 8 dB PAPR value and for 5G NR signal with 11.7 dB PAPR value, respectively.

In this paper, a Doherty power amplifier (DPA) using a novel three-port harmonic injection network (HIN) to extend its high-efficiency range is proposed. With the help of a part of the three-port HIN, which is placed between the carrier and peaking branches, the optimal drain fundamental frequency termination for the carrier device at back-off and saturation can be realized simultaneously thus enhancing the efficiency at back-off significantly. Meanwhile, this three-port HIN can also realize second harmonic drain terminations for the carrier and peaking device with the quasi-open and quasi-short circuit at the current plane, respectively. Consequently, the saturated power ratio between peaking and carrier devices is increased, which further extends the back-off range of the asymmetric drain-biased DPA. For demonstration purposes, an extended high efficiency range DPA was designed and fabricated using commercially available GaN HEMT (Cree CGH 40010F) devices. Measured results for this novel idea gave drain efficiencies better than 62.5% at 9-9.5 dB back-off point from 1.60 to 1.95 GHz.

This paper presents a novel compact Ku-band active electronically steerable antenna array design with a low-cost and integrated T/R 3D module employed for airborne synthetic aperture radar (SAR) systems. The entire system adopts 3D multilayer technology with vertical interconnection to construct the hermetically packaging RF modules. By assembling different multifunctional modules into a whole multilayer board, the 3D T/R technique greatly improves the system integration and reduces implementation cost and size. Besides, a wideband circular polarized antenna array was designed in LTCC and connected to the proposed T/R modules to form a complete AESA. The whole proposed antenna system has been fabricated and experimentally investigated. Measurement results showed very good phased array performances in terms of gain, axial ratio, and radiating patterns. The low-cost, lightweight, and low-power features exhibited by the proposed design validate its applicability for weight and power constrained platforms with great electronic steering ability.

This paper proposes a new broadband Doherty power amplifier topology with extended back‐off range. A shunted λ /4 short line or λ /2 open line working as compensating reactance is introduced to the conventional load modulation network, which greatly improves its bandwidth. Underlying bandwidth extension mechanism of the proposed configuration is comprehensively analyzed. A three‐device Doherty power amplifier is implemented for demonstration based on Cree’s 10 W HEMTs. Measurements show that at least 41% drain efficiency is maintained from 2.0 GHz to 2.6 GHz at 8 dB back‐off range. In the same operating band, saturation power is larger than 43.6 dBm and drain efficiency is higher than 53%.