Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Massimiliano Picca

dblp:202/3318 · DBLP profile ↗
← Back
2ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Storage systems · 88% Hardware reliability and fault tolerance · 8% Integrated circuit design · 4%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Storage systems › flash and SSD
flash memory
0.122009
Non-Volatile Memories for Removable Media · Proc. IEEE 2009
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003
Storage systems › flash and SSD › flash memory
NAND flash
0.112009
Non-Volatile Memories for Removable Media · Proc. IEEE 2009
Storage systems
storage reliability
0.012009
Non-Volatile Memories for Removable Media · Proc. IEEE 2009
Integrated circuit design
digital circuit design
0.012003
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003
Hardware reliability and fault tolerance › error correction
error-correcting codes
0.012003
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003
Hardware reliability and fault tolerance › redundancy
redundancy management
0.012003
An overview of logic architectures inside flash memory devices · Proc. IEEE 2003

Methods — techniques the papers use, named apart from their topics

remapping · 0.1bad block management · 0.1
YearPublicationVenuePosition
2009 Non-Volatile Memories for Removable Media
abstract
NAND Flash memory has become the preferred nonvolatile choice for portable consumer electronic devices. Features such as high density, low cost, and fast write times make NAND perfectly suited for media applications where large files of sequential data need to be loaded into the memory quickly and repeatedly. When compared to a hard disk drive, a limitation of the Flash memory is the finite number of erase/write cycles: most of commercially available NAND products are guaranteed to withstand 105programming cycles at most. As a consequence, special care (remapping, bad block management algorithms, etc.) has to be taken when hard-drive based, read/write intensive applications, such as operating systems, are migrated to Flash-memory based devices. One of the basic requirements of the consumer market for data storage is the portability of stored data from one device to the other. Flash cards are the actual solution. A Flash card is a nonvolatile ldquosystem in packagerdquo in which a NAND Flash memory is embedded with a dedicated controller. This paper presents the basic features of the NAND Flash memory and the basic architecture of Flash cards. We provide an outlook on opportunities and challenges of future Flash systems.
Rino Micheloni, Massimiliano Picca, Stefano Amato, Helmut Schwalm, Michael Scheppler, Stefano Commodaro
Proc. IEEE2
2003 An overview of logic architectures inside flash memory devices
abstract
In the past few years, the complexity of logic functions and architectures inside a flash memory device has grown in order to face the need for more complex system interfaces and to manage the increased amount of stored data. In this paper, an overview of these developments will be given. The paper is divided into sections describing areas where logic circuits play a key role: program/erase algorithms handling and user interface, redundancy management for yield enhancement, error correction codes to enhance reliability, and burst and page mode access control to enhance read bandwidth.
Andrea Silvagni, Guiseppe Fusillo, Roberto Ravasio, Massimiliano Picca, Stefano Zanardi
Proc. IEEE4