In this paper, we review and provide additional details about our progress on multilayer silicon nitride (SiN)-on-silicon (Si) integrated photonic platforms. In these platforms, one or more SiN waveguide layers are monolithically integrated onto a Si photonic layer. This paper focuses on the development of three-layer platforms for the O- and SCL-bands for very large-scale photonic integrated circuits requiring hundreds or thousands of waveguide crossings. Low-loss interlayer transitions and ultralow-loss waveguide crossings have been demonstrated, along with bilevel and trilevel grating couplers for fiber-to-chip coupling. The SiN and Si passive devices have been monolithically integrated with high-efficiency optical modulators, photodetectors, and thermal tuners in a single photonic platform.

This paper reviews developments in cascaded microresonator-based matrix switches for silicon photonic interconnection networks in many-core computing applications. Specifically, we emphasize our recently proposed 5$\times$5 matrix switch comprising two-dimensionally cascaded microring resonator-based electrooptic switches coupled to a waveguide cross-grid on a silicon chip. The cross-grid adopts low-loss low-crosstalk multimode-interference-based waveguide crossings. Such a microresonator-based matrix switch offers nonblocking interconnections among multiple inputs and multiple outputs, with the key merits of i) a tens to hundreds of micrometers-scale footprint, ii) gigabit/second-scale data transmission, iii) nanosecond-speed circuit-switching, iv) 100-$ \mu{\hbox{W}}$-scale dc power consumption per link, and v) large-scale integration for networks-on-chips applications. We analyze in detail the microring resonator-based cross-grid switch design for high-data-rate signal transmission in the context of our proposed 5$\times$5 matrix switch. We also study the feasibility of large-scale integration of the matrix switch. We report proof-of-concept experiments of a single cross-grid switch element and a 2$\times$2 matrix switch, propose design guidelines, and discuss future engineering challenges.