Demo Data from EDBT 2026 / reviewers in the wild / expert
Davide Ferrara
dblp:202/3415
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 77% Integrated circuit design · 23% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › packaging
system-in-package |
0.0 | 1 | 2009 | System in Package Feasibility Process · Proc. IEEE 2009 |
Methods — techniques the papers use, named apart from their topics
electrical analysis · 0.1design process verification · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | System in Package Feasibility ProcessabstractThis paper describes the procedure and the software process to verify the feasibility of a system in package. The process has been created to guarantee and ensure the main characteristics of such devices: a minimum time-to-market and great flexibility. A procedure is described for every step, starting from application definition to final electrical analysis. After a general introduction, all process design steps are technically analyzed; then each step of the final process check is described. Some comments and wishes are discussed in the conclusion. Pier Paolo Stoppino, Armando Conci, Tito Lessio, Davide Ferrara |
Proc. IEEE | 4 |