Demo Data from EDBT 2026 / reviewers in the wild / expert
Tom Mitchell 0003
dblp:202/4595
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Applied, interdisciplinary, general and emerging computing · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
hardware verification and test |
0.1 | 1 | 2007 | Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM · Proc. IEEE 2007 |
Electronic design automation › timing analysis
static timing analysis |
0.1 | 1 | 2007 | Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM · Proc. IEEE 2007 |
Electronic design automation › timing analysis
transistor-level timing analysis |
0.1 | 1 | 2007 | Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM · Proc. IEEE 2007 |
Electronic design automation › physical verification
electrical rule checking |
0.0 | 1 | 2007 | Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM · Proc. IEEE 2007 |
Electronic design automation › physical design
parasitic extraction |
0.0 | 1 | 2007 | Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM · Proc. IEEE 2007 |
Electronic design automation
physical design |
0.0 | 1 | 2007 | Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM · Proc. IEEE 2007 |
Methods — techniques the papers use, named apart from their topics
transistor width tuning · 0.1static noise analysis · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Transistor-Level Tools for High-End Processor Custom Circuit Design at IBMabstractIBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout. Karen Bard, Bill Dewey, Mei-Ting Hsu, Tom Mitchell 0003, Karl Moody, Vasant Rao, Ron Rose, Jeff Soreff, Steve Washburn |
Proc. IEEE | 4 |