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Gerhard Hettich

dblp:202/4624 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 61% Electronic design automation · 30% Embedded and real-time systems · 9%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware/software co-design
hardware/software partitioning
0.112007
Dynamic and Partial FPGA Exploitation · Proc. IEEE 2007
Reconfigurable computing and FPGAs › dynamic reconfiguration
partial reconfiguration
0.112007
Dynamic and Partial FPGA Exploitation · Proc. IEEE 2007
Reconfigurable computing and FPGAs › reconfigurable computing
reconfigurable system design
0.112007
Dynamic and Partial FPGA Exploitation · Proc. IEEE 2007
Embedded and real-time systems
automotive embedded systems
0.012007
Dynamic and Partial FPGA Exploitation · Proc. IEEE 2007

Methods — techniques the papers use, named apart from their topics

bus system design · 0.1LUT-based communication primitive · 0.1
YearPublicationVenuePosition
2007 Dynamic and Partial FPGA Exploitation
abstract
Today's field programmable gate array (FPGA) architectures, like Xilinx's Virtex-II series, enable partial and dynamic run-time self-reconfiguration. This feature allows the substitution of parts of a hardware design implemented on this reconfigurable hardware, and therefore, a system can be adapted to the actual demands of applications running on the chip. Exploiting this possibility enables the development of adaptive hardware for a huge variety of applications. A novel method for communication interfaces using look up table (LUT)-based communication primitives enables an exact separation of reconfigurable parts and a fast and intelligent bus-system. A new adaptive software/hardware reconfigurable system is presented in this paper, using a real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA to present results.
Jürgen Becker 0001, Michael Hübner 0001, Gerhard Hettich, Rainer Constapel, Joachim Eisenmann, Jürgen Luka
Proc. IEEE3