We propose a Diffusion-Enhanced Graph Transformer (DEGT) for analog circuit optimization that overcomes the limitations of traditional vector- and graph-based approaches. Conventional methods struggle to capture the complex connectivity of analog circuits and often require expert-imposed heuristic constraints on the sizing of some transistors to greatly reduce the searching space. In contrast, our method introduces three key innovations. First, an enhanced graph representation combined with a transformer architecture conveys circuit information to the machine learning network without any loss, enabling effective incremental knowledge transfer across various circuit designs. Second, the proposed DEGT quantifies the influence of each device by considering connection distances and path configurations, thereby providing a comprehensive, topology-aware representation of device interactions. Third, a violation handling method autonomously trains non-functional regions in the design space, eliminating the need for expert-imposed constraints or circuit classifications. Experimental evaluations demonstrate that the proposed optimizer consistently improves the figure of merit for a circuit with each round of incremental knowledge transfer using data from different circuits. These results highlight the potential of our approach to advance autonomous analog circuit design by reducing the reliance on expert intervention and improving overall optimization performance.

Finding an optimal point in the design space of analog circuits requires a substantial time-consuming effort even for skillful circuit designers. There have been extensive studies on automated sizing of transistors in analog circuits based on machine learning (ML) algorithms. However, the previous approaches suffer from lack of expandability and necessitate an inevitable retraining process of the given model to apply for optimization of different circuits. The graph-based representation of a circuit with reinforcement learning (RL) achieved a knowledge transfer when optimizing the same circuit with different process technologies. However, it can be hardly applied to different circuit topologies due to the failure of generalizing the training of RL agent. This paper introduces Trans-Net, an analog circuit optimizer that is capable of supporting the knowledge transfer across different circuits as well as different process technologies with a circuit representation that defines the circuit topology by one-to-one mapping from SPICE netlist. The proposed analog circuit optimizer successfully supports multiple circuits within a single ML model, showcasing its effectiveness on five different circuit topologies across three different process technologies.

Graph Convolutional Networks (GCNs) have demonstrated their efficacy in various real-world applications such as social networks and recommendation systems. Accelerating GCNs presents unique challenges due to their large number of nodes, sparse and heavily skewed connections. The reordering of the adjacency matrix has been the main strategy to effectively reduce the amount of re-access. Existing techniques of the reordering are categorized into i) degree-based sorting to identify high-degree nodes so that their data could be stored in the cache and ii) graph partitioning to maximally reuse the clustered data. However, as connections among the nodes vary significantly, processing various GCNs with a single strategy would cause performance degradation. This paper presents a software/hardware co-optimized platform for processing of general GCNs. We propose a hybrid scheme in the graph reordering that combines a sorting and a clustering in an adaptively optimized two-way partitioning. The two-way partitioning enables an efficient allocation of the on-chip cache memory space to reduce off-chip memory access by 4-to-12 %. The implemented accelerator in 28nm demonstrates full functionalities with improved energy-efficiency by$2.2-\text{to}-3.7\times$compared to the previous GCN accelerators.

State-of-the-art compact models such as MobileNets and EfficientNets are structured using a linear bottleneck and inverted residuals. Hardware architecture using a single dataflow strategy fails to balance the required memory bandwidth with the given computational resources. This work presents a heterogeneous dual-core accelerator that performs a block-wise pipelined process as a unit using a bottleneck-stationary (BS) dataflow. The BS greatly relieves the requirement on DRAM bandwidth and on-chip SRAM capacity. A look-behind-only attention is also proposed as a co-optimized algorithm. Compared to the state-of-the-art hardware scheme, the proposed accelerator demonstrates a reduction of 1.8-$2.9\times $in latency and 2.2-$3\times $in energy consumption, respectively.For verification, the accelerator with a 16-bit integer precision was implemented using 28nm CMOS process. Measurements show energy efficiencies of 0.5-to-3.75 TOPS/W in a supply voltage range of 0.55-to-1.15V.