Today, testing of AMS circuits needs to improve quality towards ppb test escape levels as well as decrease the test development time to reduce the IC lead time. A defect-oriented solution can improve quality by focusing on structural tests that can detect defects more efficiently than traditional functional tests, while test reuse can decrease test development time on ICs built with reusable IP blocks. A defect-oriented built-in self-test (BIST) approach integrates both solutions. This paper proposes a test development methodology for analog IP blocks based on such defect-oriented BIST framework. The methodology allows for achieving the target defect coverage at the lowest possible cost. Co-designing the IP with the DfT structures allows accounting for any non-idealities that the DfT may add to the IP. Test structures cost is limited by using low-cost signal generation and a new output response analyzer (ORA). The proposed methodology is demonstrated on two case studies. The results show that coverages higher than 90% are possible using a simple digital pulse signal and an ORA with only 4 bits of accuracy, while coverages higher than 95% are possible with 6 bits, offering a good trade-off between coverage and cost.

In industry-scale integrated circuit (IC) production, continuous improvements in processing and testing have resulted in defect test escape rates gradually reaching levels below 100 PPB for analog and mixed-signal (AMS) ICs. Newer methodologies are needed to reduce these rates even further in light of the ever-tightening reliability requirements in the automotive industry while minimizing additional costs. Detecting latent defects is a major challenge today. A research experiment was conducted to assess and improve the latent defect test escape rate of industry-scale AMS testing at test time. This experiment altered the IC production process to artificially introduce latent gate oxide defects of different sizes and locations in a commercially available automotive IC in a 350-nm high-voltage BCD process currently in production. The standard industrial test program was able to detect 58.4% of the latent defects at a yield loss of 6.2%. The latent defect detection rate has been improved to 95.5% at an additional yield loss of only 0.8% using support vector machine (SVM) classifiers on the dataset of measurements resulting from the standard test program. This type of classifier is chosen for its optimal use of available data. The results show that a significant gain in coverage is possible without adding extra tests. In the experiment, testing at high temperatures (HOT) proved crucial in achieving this coverage benefit. Furthermore, while traditional tests mainly detect latent defects close to the source of transistors, the SVM approach significantly improves the detection of pinhole latent defects closer to the drain.

With quality and reliability requirements moving toward the ppb level, latent defects have become a major bottleneck. This article introduces a new metric, called difference in the distance to mean value (DDtM), that exploits the latent defect information present in measurements of an integrated circuit (IC) carried out under more than one operating condition. The use of this metric improves the latent defect coverage provided by post-processing (PP) techniques at no additional cost. The DDtM tracks, for each measured variable, shift in the distance from the IC’s measured value to the population mean value when the conditions applied to the IC change. To demonstrate the effectiveness of the DDtM metric, two circuits that are part of an industrial mixed-signal IC are used as case studies. The results show that the use of the DDtM metric improves latent defect coverage regardless of the PP technique used, providing up to a 60% improvement in coverage compared to the results obtained using the same measurement data but without DDtM.

In this work, a novel outlier detection method is presented in which the data from the visual inspection of manufactured wafers are combined with the data from the electrical test. Three different implementations are built with increasing complexity in order to detect outliers that are not detected by a traditional outlier detection method such as the Dynamic Part Average Testing (DPAT). The screening parameters are constructed as a reformulation of the DPAT formulas, integrating information from visual inspection and the layout of the used product. The proposed VEDPAT algorithms are applied to a total of 25 wafers spread over 5 lots in order to compare their effectiveness. The results show that a method that combines the available information with the layout is able to effectively screen out outliers at the expense of only a very small yield loss. Also, details and microscope pictures of the false alarms and outliers detected by the method are presented.

With tightening automotive IC production test requirements, test escape rates need to decrease down to the 10 PPB level. To achieve this for mixed-signal ICs, advanced multivariate statistical techniques are needed, as the defects in the test escapes become increasingly more difficult to detect. Therefore, this paper proposes applying a cascade of advanced statistical techniques to identify measurements that can be used as predictors to flag future potential failures at test time with minimal misclassification of good devices. The approach uses measurement data from the ATE wafer probe tests and is also able to identify the likely location of the defect using only these measurements. The cascade has four steps: 1) remove bias and spatial patterns within the data, 2) divide the different tests into relevant groups, 3) reduce the dimensionality of each group, and 4) perform multiple regression to find the predictor values and use these values to compute an outlier score for each chip under test. As there is a risk of overfitting the outlier score, the number of predictors used is kept to a minimum. The effectiveness of the proposed methodology is demonstrated using test data from an industrial production chip with eight field-return cases. Predictors have been found that retroactively allowed the identification of these chips, with an average of 5% false classification of good devices, i.e. devices not returned from the field. In addition, the selected predictors corresponded to where the defects are located according to failure analysis of the field returns.

Automotive applications are driving the need for better IC quality, reliability, and functional safety, in a market that is cost-sensitive and rapidly changing. The goals are to deliver zero defective parts without time-consuming and expensive burn-in, and satisfy functional safety requirements. This paper shows how measuring the percentage of circuit elements that are subject to sufficient stress during testing, especially across thin oxides, can be used as a criterion to drive improving the circuit's reliability. The paper also shows how to more accurately compute a circuit's ISO 26262 metrics using activity-based defect likelihoods. Simulation results are provided for an ITC'17 mixed-signal benchmark circuit (bandgap + LDO + voltage monitor) and for an industrial automotive product IC, showing the potential of the method to improve reliability and functional safety of analog/mixed-signal ICs.

Test detection of lifetime failures due to latent defects is a necessity to reach the tightening quality requirements of automotive systems. This paper presents a pinhole latent defect model, together with a simulation workflow, that can be used to develop defect-oriented analog test approaches for pinhole latent defects. This work also defines the latent defect coverage and activation coverage, providing the means to compare different test methods under the same rules. Furthermore, a circuit taken from an industrial mixed-signal IC is used as case study. The results show that the typically applied specification tests are insufficient to detect latent defects. It is demonstrated that the coverage can be increased by adding well-selected tests in combination with voltage stress techniques. Doing so, the coverage for the case study is increased by 15x.

Safety-critical and mission-critical systems, such as airplanes or (semi-)autonomous cars, are relying on an ever-increasing number of embedded integrated circuits. Consequently, there is a need for complete defect coverage during the testing of these circuits to guarantee their functionality in the field. In this context, reducing the escape rate of defects during production testing is crucial, and significant progress has been made to this end. However, production testing using automatic test equipment is subject to various measurement parasitic variations, which may have a negative impact on the testing procedure and therefore limit the final defect coverage. To tackle this issue, this article proposes an improved test flow targeting increased analog defect coverage, both at the system and block levels, by analyzing and improving the coverage of typical functional and structural tests under these measurement variations. To illustrate the flow, the technique of inserting a pseudo-random signal at available circuit nodes and applying machine learning techniques to its response is presented. A DC-DC converter, derived from an industrial product, is used as a case study to validate the flow. In short, results show that system-level tests for the converter suffer strongly from the measurement variations and are limited to just under 80% coverage, even when applying the proposed test flow. Block-level testing, however, can achieve only 70% fault coverage without improvements but is able to consistently achieve 98% of fault coverage at a cost of at most 2% yield loss with the proposed machine learning–based boosting technique.

The integration of increasingly more complex and heterogeneous SOCs results in ever more complicated demands for the verification of the system and its underlying subsystems. Pre-silicon design validation as well as post-silicon test generation of the analog and mixed-signal (AMS) subsystems within SOCs proves extremely challenging as these subsystems do not share the formal description potential of their digital counterparts. Several methods have been developed to cope with this lack of formalization during AMS pre-silicon validation, including model checkers, affine arithmetic formalisms and equivalence checkers. However, contrary to the industrial practice for digital circuits of using formal verification and ATPG tools, common industry practice for analog circuits still largely defaults to simulation-based validation and test generation. A new formal digital-inspired technique, called AMS-QED, can potentially solve these issues in analog and mixed-signal verification.

The test and design methodology currently used to develop automotive mixed-signal integrated circuits, is not sufficient to achieve the <; 10 PPB quality target. In particular it does not allow to activate and detect all latent defects, which are a significant cause of vehicle failures in the field. This paper discusses whether full burn-in will be needed in order to meet the quality goal, or whether Vstress in combination with a defect activation coverage methodology will do the job.

Guaranteeing correct and reliable cyber-physical systems requires testing of analog/mixed-signal ICs towards low defect escape rates, below the ppm level. It also requires guaranteeing correct functioning over the product lifetime. However, there are not yet industry-wide automated tools that can generate adequate tests to this end for analog/mixed-signal ICs, like it is currently the case with digital ICs. This paper presents different methods and algorithms that target decreasing defect test escapes in analog/mixed-signal ICs. These methods are based on structural testing for defects, they use fault analysis tools for escape rate analysis and employ DfT structures to increase test coverage, which reduces test escape rate. Furthermore, these structures activate possible latent defect, that may pose threats during the lifetime of integrated circuits.

The quality level of the analog parts in mixed-signal ICs lags behind the below-part-per-million escape rates of the digital core. The reason is that analog blocks in these ICs have high test escape rates as a result of the typical testing based on performance specifications. Test point selection/insertion techniques have been proposed to solve this problem by offering increased observability. However, their effectiveness in practice is still limited due to the lack of a commonly accepted methodology to make probing of internal nodes in analog circuitry possible. This paper presents a low-cost and highly parallel DfT technique based on inserting testing diodes to internal circuit nodes, which enables those test point selection algorithms at low cost. An industrial case study demonstrates 90.4% fault coverage value with a very small overhead in area and test time.

An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability algorithm gives the trade-off between fault activation rate, silicon area cost and testing time for different test solutions. Both CMOS and DMOS devices are handled to accommodate the testing of high-voltage circuits. When applied to latent gate oxide defects in a voltage regulator circuit, an activation rate of up to 76.7% is achieved. In comparison, the stressing by increased supply voltage only reaches 28%. For the same testing time, this improvement comes at the expense of three additional stress transistors with a silicon area overhead of less than 1%.

The quality level of mixed-signal ICs lags behind the below-part-per-million defect test escape rates of digital ICs, as a result of the traditional testing based on performance specifications. Methods increasing the controllability to solve the problem of the low fault coverage of analog and mixed-signal circuits are in practice limited due to the excessive area overhead they require and their impact on the normal circuit operation. This paper presents a non-intrusive method to improve the controllability using light as an activation mechanism. The necessary simulation models are introduced to use the proposed method in the context of a defect-oriented test approach. This work also describes a workflow which enables the application of the method to large-scale industrial circuits. Finally, effective results are shown on an industrial mixed-signal front-end circuit under test (CUT) demonstrating around 27% increase in the number of detectable defects.