Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Vanya Yaneva

dblp:202/8463 · DBLP profile ↗
← Back
5ranked-venue papers
4as first author
1since 2021 · last 2022
0000-0003-3804-8088ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 5 · 4 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
2 papers
Software testing · 100%
Computer architecture, parallel and distributed computing, and storage systems
2 papers
GPUs and heterogeneous computing · 87% Embedded and real-time systems · 13%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software testing
test execution
0.622017
ParTeCL: parallel testing using OpenCL · ISSTA 2017
Compiler-assisted test acceleration on GPUs for embedded software · ISSTA 2017
GPUs and heterogeneous computing
GPU computing
0.622017
ParTeCL: parallel testing using OpenCL · ISSTA 2017
Compiler-assisted test acceleration on GPUs for embedded software · ISSTA 2017
Software testing › test execution
parallel testing
0.312017
ParTeCL: parallel testing using OpenCL · ISSTA 2017
Embedded and real-time systems
embedded software
0.112017
Compiler-assisted test acceleration on GPUs for embedded software · ISSTA 2017

Methods — techniques the papers use, named apart from their topics

compiler-assisted parallelization · 0.6OpenCL · 0.6
YearPublicationVenuePosition
2022 GPU acceleration of finite state machine input execution: Improving scale and performance
abstract
Summary Model‐based development is a popular development approach in which software is implemented and verified based on a model of the required system. Finite state machines (FSMs) are widely used as models for systems in several domains. Validating that a model accurately represents the required behaviour involves the generation and execution of a large number of input sequences, which is often an expensive and time‐consuming process. In this paper, we speed up the execution of input sequences for FSM validation, by leveraging the high degree of parallelism of modern graphics processing units (GPUs) for the automatic execution of FSM input sequences in parallel on the GPU threads. We expand our existing work by providing techniques that improve the performance and scalability of this approach. We conduct extensive empirical evaluation using 15 large FSMs from the networking domain and measure GPU speed‐up over a 16‐core CPU, taking into account total GPU time, which includes both data transfer and kernel execution time. We found that GPUs execute FSM input sequences up to 9.28× faster than a 16‐core CPU, with an average speed‐up of 4.53× across all subjects. Our optimizations achieve an average improvement over existing work of 58.95 % for speed‐up and scalability to large FSMs with over 2K states and 500K transitions. We also found that techniques aimed at reducing the number of required input sequences for large FSMs with high density were ineffective when applied to all‐transition pair coverage, thus emphasizing the need for approaches like ours that speed up input execution.
Vanya Yaneva, Ajitha Rajan, Christophe Dubach
Softw. Test. Verification Reliab.1
2018 Accelerated Finite State Machine Test Execution Using GPUs
abstract
Model-based development has emerged as a popular approach aiding automation of the software development process, where software is implemented and tested based on a model of the required system. Finite State Machines (FSMs) are a widely used model representation for a variety of systems, including control systems, signal processing and communications protocols. Ensuring that the model accurately represents the required behaviour involves the generation and execution of a large number of tests that is time consuming and expensive. In this paper, we focus on test execution and propose exploiting Graphics Processing Units (GPUs) for accelerating FSM testing by executing the tests in parallel on GPU threads. Our approach includes methods to encode the FSM efficiently and optimise the layout of tests in GPU memory for fast execution. We compare speedup achieved by our approach against parallel test execution on a multi-core CPU with 16 cores. We also assess the improvement in speedup using the proposed FSM encoding and test layouts. We use large FSMs from the networking domain and a large industry FSM from Keysight, who provide electronic measurement solutions, in our evaluation. We accelerate the execution of test suites providing all-transition pair coverage for each of the FSMs. Speedup achieved is subject to characteristics of the FSM and associated tests, and is greatly improved with efficient FSM encoding and test layout in memory. We find our approach on the GPU achieves a maximum test execution speedup of 12× over a 16-core CPU.
Vanya Yaneva, Arnav Kapoor, Ajitha Rajan, Christophe Dubach
APSEC1
2018 Assessing the effect of data transformations on test suite compilation
abstract
Background. The requirements and responsibilities assumed by software has increasingly rendered it to be large and complex. Testing to ensure that software meets all its requirements and is free from failures is a difficult and time-consuming task that necessitates the use of large test suites, containing many tests. Large test suites result in a corresponding increase in the size of the test code that sets up, exercises and verifies the tests. Time needed to compile and optimise the test code becomes prohibitive for large test code sizes.
Panagiotis Stratis, Vanya Yaneva, Ajitha Rajan
ESEM2
2017 Compiler-assisted test acceleration on GPUs for embedded software
abstract
Embedded software is found everywhere from our highly visible mobile devices to the confines of our car in the form of smart sensors. Embedded software companies are under huge pressure to produce safe applications that limit risks, and testing is absolutely critical to alleviate concerns regarding safety and user privacy. This requires using large test suites throughout the development process, increasing time-to-market and ultimately hindering competitivity.
Vanya Yaneva, Ajitha Rajan, Christophe Dubach
ISSTA1
2017 ParTeCL: parallel testing using OpenCL
abstract
With the growing complexity of software, the number of test cases needed for effective validation is extremely large. Executing these large test suites is expensive and time consuming, putting an enormous pressure on the software development cycle. In previous work, we proposed using Graphics Processing Units (GPUs) to accelerate test execution by running test cases in parallel on the GPU threads. However, the complexity of GPU programming poses challenges to the usability and effectiveness of the proposed approach.
Vanya Yaneva, Ajitha Rajan, Christophe Dubach
ISSTA1