EDBT 2026 Demo / reviewers in the wild / expert
Jun-Zhi Yang
dblp:202/9474
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design › placement › cell placement
datapath placement |
0.3 | 1 | 2017 | Graph-Based Logic Bit Slicing for Datapath-Aware Placement · DAC 2017 |
Electronic design automation
physical design |
0.3 | 1 | 2017 | Graph-Based Logic Bit Slicing for Datapath-Aware Placement · DAC 2017 |
Electronic design automation › physical design
placement |
0.3 | 1 | 2017 | Graph-Based Logic Bit Slicing for Datapath-Aware Placement · DAC 2017 |
Methods — techniques the papers use, named apart from their topics
simulated annealing · 0.3network flow · 0.3bipartite edge-cover · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | Graph-Based Logic Bit Slicing for Datapath-Aware PlacementabstractExtracting similar datapath bit slices which handle highly parallel bit operations can help a modern placer to obtain better solutions for datapath-oriented designs. A current state-of-the-art datapath bit slicing method achieves the best extraction results using a network-flow-based algorithm. However, this work has two major drawbacks: (1) it extracts only a limited number of bit slices for datapaths with different I/O widths, which are commonly seen in real designs, and (2) it does not consider bit-slice similarity, which is an important feature for placement considering datapaths. To remedy these drawbacks, we present (1) a balanced bipartite edge-cover algorithm to fully slice a datapath with different I/O widths, and (2) a simulated annealing scheme to further improve bit-slice similarity, while maintaining fully-sliced structures. Compared with the state-of-the-art work, experimental results show that our slicing algorithm extracts more bit slices with similar structures, and helps a leading academic placer achieve averagely 5% smaller routed wirelength. The results also validate the high correlation between datapaths and structure regularity/similarity. Chau-Chin Huang, Bo-Qiao Lin, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang |
DAC | 6 |