Multimodal Large Language Models (MLLMs) have become widely deployed, yet their safety alignment remains fragile under adversarial inputs. Previous work has shown that increasing inference steps can disrupt safety mechanisms and lead MLLMs to generate attacker-desired harmful content. However, most existing attacks focus on increasing the complexity of the modified visual task itself and do not explicitly leverage the model’s own reasoning incentives. This leads to them underperforming on reasoning models (Models with Chain-of-Thoughts) compared to non-reasoning ones (Models without Chain-of-Thoughts). If a model can think like a human, can we influence its cognitive-stage decisions so that it proactively completes a jailbreak? To validate this idea, we propose GAMBIT (Gamified Adversarial Multimodal Breakout via Instructional Traps), a novel multimodal jailbreak framework that decomposes and reassembles harmful visual semantics, then constructs a gamified scene that drives the model to explore, reconstruct intent, and answer as part of winning the game. The resulting structured reasoning chain increases task complexity in both vision and text, positioning the model as a participant whose goal pursuit reduces safety attention and induces it to answer the reconstructed malicious query. Extensive experiments on popular reasoning and non-reasoning MLLMs demonstrate that GAMBIT achieves high Attack Success Rates (ASR), reaching 92.13% on Gemini 2.5 Flash, 91.20% on QvQ-MAX, and 85.87% on GPT-4o, significantly outperforming baselines. Warning: This paper contains unsafe and offensive examples.

This paper presents an efficient multi-fidelity Bayesian optimization approach for analog circuit synthesis. The proposed method can significantly reduce the overall computational cost by fusing the simple but potentially inaccurate low-fidelity model and a few accurate but expensive high-fidelity data. Gaussian Process (GP) models are employed to model the low- and high-fidelity black-box functions separately. The nonlinear map between the low-fidelity model and high-fidelity model is also modelled as a Gaussian process. A fusing GP model which combines the low- and high-fidelity models can thus be built. An acquisition function based on the fusing GP model is used to balance the exploitation and exploration. The fusing GP model is evolved gradually as new data points are selected sequentially by maximizing the acquisition function. Experimental results show that our proposed method reduces up to 65.5% of the simulation time compared with the state-of-the-art single-fidelity Bayesian optimization method, while exhibiting more stable performance and a more promising practical prospect.

Conventional yield optimization approaches rely on accurate yield estimation for given design parameters, which would be computational intensive. In this paper, a novel Bayesian yield optimization approach is proposed for analog and SRAM circuits. An equivalent a problem is formulated via applying Bayes' theorem on the augmented yield problem. The yield optimization problem is converted to identifying the design parameters with maximal probability density conditioning on the event that the corresponding circuit is "pass". Gaussian kernel density estimation is employed to approximate the conditional probability, and a multi-start-point based EM-like algorithm is proposed to solve the equivalent problem efficiently Compared with the state-of-the-art yield optimization approaches, the proposed method can significantly reduce the number of circuit simulations with comparable optimization accuracy by avoiding repetitive yield estimations.

The printability problem of chip making becomes challenging in advanced process nodes. At present, various lithography technologies such as multiple patterning (MP), directed self-assembly (DSA), electron beam (e-beam), and their combinations are being considered. In this paper, the corresponding layout decomposition problems for contact/via generation are studied. In particular, we investigate the simultaneous DSA template and e-beam throughput optimization. First, we present an exact method based on an ILP formulation. Then, a graph-based algorithm is developed. The co-optimization problem for DSA double patterning with e-beam is formulated as a minimum hitting set problem. A primal-dual based algorithm is then derived for solving the problem effectively. Experimental results show that compared with a two-stage method, our method can achieve around 20.6% throughput improvement and 18.7% template cost reduction.

End cutting 1D layout process is a promising candidate for sub-10nm process nodes. To be correctly manufactured, any pair of end cuts must be either merged/aligned or apart from each other with at least a minimum distance. This constraint adversely affects the manufacturability, especially when the end cuts have to be solely printed with the conventional lithography technology. To improve the manufacturability, recent works start to consider the constraint in early stages, such as physical design. In this paper, we propose a heuristic grid-based detailed routing algorithm for the end cutting 1D layout process. One important issue of the routing algorithm is how to represent the routing resources, especially for the end cuts. In the proposed algorithm, this issue is addressed by maintaining a directed routing graph. On the routing graph, new end cuts are initially located by a regular shortest path algorithm. Since the routing resources are correctly represented with the routing graph, the new end cuts are not in conflict with the existing end cuts. To further resolve the conflicts among the new end cuts, each segment of the wire is sequentially legalized. Experimental results indicate that compared with an intuitive two-stage method, the proposed algorithm can achieve higher solution quality with much less runtime.

Spectral graph sparsification aims to find an ultra-sparsified matrix which can be used as a good preconditioner for the original matrix. Low-stretch spanning tree could be constructed for this purpose. The relative condition number with the low-stretch spanning tree is bounded, which ensures the convergence of the PCG method with low-stretch spanning tree as preconditioner. Recently, spectral perturbation analysis is proposed to add a group of spectral critical edges to the spanning tree. The relative condition number can thus be further reduced. In this paper, we proposed a Krylov-subspace based spectral perturbation analysis to find the spectral critical edges. Compared with the traditional power-iteration-based approach, our proposed method can significantly improve the convergence of spectral perturbation analysis and thus accelerate the procedure of constructing the ultra-sparsified preconditioner.

Return-Address Stack (RAS) has been widely used in modern high-performance microprocessor to predict the return address of a routine. But speculative execution frequently corrupts the RAS, making repair mechanisms necessary. In this paper, based on analysis of RAS activities after misprediction and current RAS repair mechanisms, an effective return address prediction structure called Self-Aligning Return-Address Stack (SARAS) is proposed. SARAS is composed of a classical RAS, a self-aligning queue and a top-of-stack counter. The self-aligning queue records the contents popped from RAS for recovery. The top-of-stack counter tracks the latest correct position of the top-of-stack pointer. The experiment results show that SARAS can reduces hardware-cost and enhances prediction accuracy, with a 32-entry stack, the average prediction accuracy of SARAS is nearly 100%, improving performance by 3.91% up to 11.27% over the conventional checkpointing repair mechanisms for RAS. At the same hardware budget, this speedup is even higher.