Demo Data from EDBT 2026 / reviewers in the wild / expert
Kuan-Jung Chen
dblp:202/9575
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 2018
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 81% Interconnection networks and networks-on-chip · 19% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip
optical network-on-chip |
0.3 | 1 | 2018 | PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip · DAC 2018 |
Electronic design automation
design for manufacturability |
0.3 | 1 | 2017 | Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification · DAC 2017 |
Electronic design automation › physical design › layout pattern analysis
layout pattern matching |
0.3 | 1 | 2017 | Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification · DAC 2017 |
Electronic design automation › physical design › lithography
lithography hotspot detection |
0.3 | 1 | 2017 | Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification · DAC 2017 |
Electronic design automation
physical verification |
0.3 | 1 | 2017 | Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification · DAC 2017 |
Electronic design automation
physical design |
0.1 | 1 | 2018 | PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip · DAC 2018 |
Electronic design automation › physical design
placement and routing |
0.1 | 1 | 2018 | PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip · DAC 2018 |
Electronic design automation › design for manufacturability › design for yield
yield enhancement |
0.1 | 1 | 2017 | Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification · DAC 2017 |
Methods — techniques the papers use, named apart from their topics
two-stage pattern matching · 0.3set cover · 0.3clip shifting · 0.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2018 | PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chipabstractOptical networks-on-chips (ONoCs) have become a promising solution for the on-chip communication of multi-and many-core systems to provide superior communication bandwidths, efficiency in power consumption, and latency performance compared to electronic NoCs. Serving as the critical part of ONoCs, an optical router composed of waveguides and photonic switching elements (PSEs) routes signals between two hubs or between a hub and a memory controller. Many studies focus on developing efficient architectures of optical routers, while their physical implementation that can seriously deteriorate the quality of the architectures is rarely addressed. The existing automatic place-and-route tools suffer from considerable insertion loss due to many waveguide crossings outside of PSEs, which leads to huge power consumption of laser sources. By observing that the logic schemes of most optical routers are actually planar, we develop a concurrent PSE placement and waveguide routing flow, called PlanarONoC, that guarantees optimal solutions in terms of crossings for planar logic schemes. Experimental results show that the proposed flow reduces the maximum insertion loss by 37% on average, guarantees no waveguide crossing outside of PSEs, and performs much more efficient compared to the state-of-the-art work. Yu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li 0005, Ulf Schlichtmann |
DAC | 2 |
| 2017 | Minimizing Cluster Number with Clip Shifting in Hotspot Pattern ClassificationabstractWith the rapid advance of semiconductor process technologies, layout features in integrated circuits (ICs) become highly prone to process variations. Lithography hotspots are a set of problematic layout patterns with poor printability even if they pass design rule checking (DRC). These hotspots need to be detected and fixed as early as possible in the design flow to improve manufacturability and yield. While most of existing studies focus on hotspot detection, hotspot pattern classification is rarely addressed but plays an important role in determining the efficiency of hotspot detection. In hotspot pattern classification, similar hotspots are classified into a cluster with tolerance constraints, and a representative hotspot is chosen for each cluster for future application. To minimize the problem size of subsequent hotspot detection, the number of clusters, and thus the number of representative hotspots, should be minimized. In this paper, a clip shifting method is adopted to further reduce the cluster number during hotspot classification. We propose a two-stage pattern matching algorithm flow and derive optimal solutions by solving a set cover problem. Experiment results show that our flow can reduce the cluster number by about 30% compared to reference results in 2016 CAD Contest at ICCAD. Kuan-Jung Chen, Yu-Kai Chuang, Bo-Yi Yu, Shao-Yun Fang |
DAC | 1 |