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Sai Ram Dheeraj Lokam

dblp:202/9595 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 75% Distributed systems · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Distributed systems › fault tolerance
checkpointing
0.312017
InCheck: An In-application Recovery Scheme for Soft Errors · DAC 2017
Hardware reliability and fault tolerance
error recovery
0.312017
InCheck: An In-application Recovery Scheme for Soft Errors · DAC 2017
Hardware reliability and fault tolerance
soft errors
0.312017
InCheck: An In-application Recovery Scheme for Soft Errors · DAC 2017
Hardware reliability and fault tolerance
software fault tolerance
0.312017
InCheck: An In-application Recovery Scheme for Soft Errors · DAC 2017

Methods — techniques the papers use, named apart from their topics

fault injection · 0.3
YearPublicationVenuePosition
2017 InCheck: An In-application Recovery Scheme for Soft Errors
abstract
An ideal solution for soft error tolerance should hide the effect of soft errors from user and provide correct results at expected time. Software solutions are attractive because they can provide flexible reliability without imposing any hardware modifications. Our investigation of state-of-the-art error recovery techniques reveals that they suffer from poor coverage (ability to detect and correctly recover from soft errors). This paper presents InCheck (In-application Checkpointing and Recovery) as an effective, safe and timely software technique for complete error coverage. The key features of InCheck are: verified register preservation, single memory location checkpoints, and safe & timely recovery. To evaluate the effectiveness of InCheck, we performed more than 210,000 fault injection experiments on different hardware components of an ARM cortex53-like processor running MiBench applications. The original and SWIFTR (state-of-the-art) protected programs suffered from 8000 and 1800 instances of wrong outputs respectively, but when protected by InCheck, there was no failure.
Moslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava
DAC2
2017 NEMESIS: A software approach for computing in presence of soft errors
abstract
Soft errors are considered as the main reliability challenge for sub-nanoscale microprocessors. Software-level soft error resilience schemes are desirable because they require no hardware modifications and their protection can be tuned based on the application requirements. However, existing software-level error tolerant schemes do not provide high-level of protection. In this work, we present NEMESIS - a compiler-level fine-grain soft error detection, diagnosis and recovery technique that can provide high degree of error-resiliency. NEMESIS runs three versions of computations and detects soft errors by checking the results of all memory write and branch operations. In the case of mismatch, NEMESIS recovery routine reverts the effect of error from the architectural state of the program and program resumes its normal execution. Our extensive μ-architectural-level fault injection experiments results show that NEMESIS transformation is able to detect all soft errors and recover from 97% of detected errors.
Moslem Didehban, Aviral Shrivastava, Sai Ram Dheeraj Lokam
ICCAD3