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Xiangyu Bi

dblp:202/9636 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 54% Memory systems · 46%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
fault diagnosis
0.312017
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique · DAC 2017
Electronic design automation › hardware verification and test
memory testing
0.312017
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique · DAC 2017
Memory systems › non-volatile memory
resistive memory
0.312017
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique · DAC 2017
Memory systems › emerging memory technologies
RRAM crossbar
0.312017
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique · DAC 2017
Electronic design automation
hardware verification and test
0.112017
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique · DAC 2017

Methods — techniques the papers use, named apart from their topics

voltage bias technique · 0.3sneak-path manipulation · 0.3SPICE simulation · 0.3
YearPublicationVenuePosition
2017 Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique
abstract
Metal-oxide resistive random access memories with a single memristor device at the crosspoint (1R RRAM) is a promising alternative to next generation storage technology due to their high density, scalability, non-volatility and low power consumption. However, the imperfect fabrication process introduces high defect rates of the nanoscale memristor devices and leads to yield degradation. In addition, sneak-paths occur in 1R RRAM crossbar that can jeaperdize the normal read/write operation. Previous work proposes voltage bias technique to eliminate the sneak-paths. Instead, in the paper, we leverage voltage bias to manipulate various distribution of sneak-paths that can screen one or multiple faults out of a 4 x 4 region of memristors at once, and consequently diagnose the exact location of each faulty memristor within three write-read operations. The SPICE simulation results highlight the effectiveness and efficiency of the proposed test method.
Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang 0002
DAC2