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Zifan Zhou

dblp:203/2042 · DBLP profile ↗
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3ranked-venue papers
2as first author
1since 2021 · last 2026
0000-0003-4251-4889ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 2 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 56% Electronic design automation · 44%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › high-level synthesis
scheduling
1.012026
Low-Overhead Scheduling for Synchronization in Large-Scale Heterogeneous Digital Twin Systems · INFOCOM 2026
Parallel and multicore computing
synchronization
1.012026
Low-Overhead Scheduling for Synchronization in Large-Scale Heterogeneous Digital Twin Systems · INFOCOM 2026

Methods — techniques the papers use, named apart from their topics

scheduling algorithm · 1.0
YearPublicationVenuePosition
2026 Low-Overhead Scheduling for Synchronization in Large-Scale Heterogeneous Digital Twin Systems
Zifan Zhou, Juaren Steiger, Yin Sun 0001, Bin Li 0014
INFOCOM1
2019 Graph-To-P4: A P4 boilerplate code generator for parse graphs
abstract
The work described in this paper presents Graph-to-P4, a toolset for generating P4 boilerplate code from parse graphs. The purpose of such a toolset is to provide a higher level of abstraction to program pipelines in order to fill the knowledge gap that some students may encounter when diving into P4. While P4 is not difficult to learn, Graph-to-P4 offers the possibility first draw parse graphs, generate P4 starter code and finally let programmers develop the specific data plane behavior (actions, tables, etc.). We have experienced that this toolset offers a smooth introduction to P4 and the intrinsic networking concepts attached to it. We show that the toolset has potential to provide a larger set of high-level abstractions (tables, actions, etc.)and an extension to provide a two-way code transformation.
Eder Ollora Zaballa, Zifan Zhou
ANCS2
2017 Analysis and implementation of packet preemption for Time Sensitive Networks
abstract
A standard priority-queuing system is capable of arranging packets with different traffic classes to guarantee a relatively low latency for the high priority traffic. However, in practical cases, severe delay may be caused by starting a large, low-priority frame ahead of a time-critical frame. In this paper, interspersed express traffic is evaluated, which enables preemption of non-time-critical transmission, in particular, the preemptive queuing system allows the cut-through transmission for critical traffic and minimizes the jitter. We analyse the performance of packet preemption through a system level simulation in Riverbed Modeler. The simulation is complemented by numerical analysis which provides the average queuing delay for both types of traffic (preemptable and express). Furthermore, the paper describes an approach to implement the packet preemption solution on an FPGA in VHDL, which illustrates the complexity of hardware implementation.
Zifan Zhou, Ying Yan 0001, Sarah Ruepp, Michael S. Berger
HPSR1