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Mei-Yen Chiu

dblp:203/3525 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › lithography
layout decomposition
0.312017
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Electronic design automation › physical design › lithography
multiple patterning lithography
0.312017
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017
Electronic design automation
physical design
0.312017
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2017

Methods — techniques the papers use, named apart from their topics

integer linear programming · 0.3boolean satisfiability · 0.3
YearPublicationVenuePosition
2017 A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning
abstract
Self-aligned triple patterning (SATP) lithography is one of the most promising technologies for next-generation semiconductor manufacturing process. Self-aligned patterning attracts much interest because of its significant advantage over the litho-etch-litho-etch patterning in reducing the overlay problem in lithography. However, pattern decomposition in SATP is challenging due to its counterintuitive mask synthesis. It remains relatively unstudied and its practical solutions remain to be proposed. This paper proposes an effective algorithm for SATP layout decomposition without grid-based quantization and thus substantially reduces the number of variables and constraints in solution search. Boolean satisfiability (SAT) and integer linear programming (ILP) are exploited for efficient computation. In addition to deriving high-quality layout decomposition solutions with overlay minimization, our method also allows nondecomposable spot identification to facilitate layout rectification. Experimental results demonstrate the superiority of our method compared to prior work and show the relative advantages of SAT and ILP formulations.
Hsiao-Lei Chien, Mei-Yen Chiu, Jie-Hong Roland Jiang
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2