Next-generation Internet of Medical Things (IoMT) must balance efficient local decision-making with strong privacy protection for remote monitoring and diagnosis. However, the resource constraints of IoMT devices make this difficult. This paper introduces a novel bio-signal encoder within the hyperdimensional computing (HDC) framework. It leverages inherent transistor variations for physically unclonable encoding. This technique is called variation-based analog entropy (VAE). VAE reduces memory footprint and power consumption while enhancing security. It offers a scalable, energy-efficient solution that addresses IoT’s resource limitations while ensuring secure, intelligent healthcare applications.The VAE cell achieves high entropy robustness (30.23-57.76 dB signal-to-noise ratio) with only a 10-transistor footprint. It reduces HDC vector dimensions by 14.3× and improves accuracy by 2%. Compared to an SRAM baseline, it shrinks encoder area by 1.3-4.4× and cuts leakage power by 327×. Custom analog circuits for entropy management eliminate data conversion, boosting energy efficiency to 48.5 nJ per query. Evaluations on experimentally collected bio-fluid data demonstrate classification accuracy of 94.9 % and 97.6 % in 5-class and 3-class viscosity sensing, respectively. This highlights the potential of the system for IoMT applications. Furthermore, the VAE significantly enhances security, lowering attacker-restored data peak SNR by 16 dB, and making unauthorized recovery indistinguishable.

Hyperdimensional computing (HDC) is a bio-inspired machine learning paradigm utilizing hyperdimensional spaces for data representation. HDC significantly improves the ability to learn from sparse data and enhances noise robustness, and also enables parallel computation. Despite these advantages, HDC's reliance on high dimensionality and operational simplicity can lead to increased hardware costs and potential security vulnerabilities. This paper introduces a novel HDC encoding strategy using variation-based analog entropy (VAE), aiming to reduce memory footprint, lower power/energy consumption, and enhance security with physically-unclonable entropy generation. The VAE cell, with high entropy robustness (30.23 -- 57.76 dB SNR) and a small footprint (10 transistors), allows HDC to achieve a 14.3× reduction in vector dimensions, a 4.4× decrease in unit entropy cell area, and a 2% increase in accuracy compared to binary/multi-bit HDC. These benefits lead to a 1.3 -- 4.4× area and a 327× leakage power reduction when compared to an SRAM baseline. We have designed custom low-power circuits that enable end-to-end analog entropy storage, distribution management, binding, permutation, and bundling. This analog implementation prevents data conversion during feature vector encoding, thereby significantly enhancing energy efficiency (48.5nJ per query). Furthermore, with hardware-secured basis vectors, data security is significantly improved, as evidenced by the markedly degraded visual distinguish-ability of retrieved image data and maximum of 11 dB lower PSNR.

To enhance AI robustness of mission-critical biomedical applications, Bayesian Neural Networks (BNNs) are instrumental for their structured approach to AI uncertainty estimation. However, implementing BNNs on edge devices is challenging due to significant resource demands for dynamic model updates and extensive inference sampling. Addressing this, we introduce a novel mixed-signal Compute-in-Memory with Entropy (CIE) hardware architecture that segregates dynamically-generated weights into analog entropy and digital parameters within a compute-in-memory framework, greatly reducing hardware overhead. We conducted thorough evaluations of the CIE architecture, assessing its performance against varying hardware imperfections, such as digital quantization errors, analog distribution imperfections, and device process variations, with a focus on both general and specialized tasks like Ventricular Arrhythmia (VA) detection. Our contributions include (1) a generic BNN acceleration strategy suitable for various CIM techniques and emerging devices, (2) a custom circuit design that improves hardware efficiency by 19.2×-440× compared to existing BNN accelerators, (3) a CIE-based BNN for VA detection enhancing accuracy, reducing uncertainty estimation time and energy/latency to 1.29μJ/1.55ms, and (4) identification of tolerable quantization error and device variation limits for BNNs in uncertainty estimation.

With the rising threats of side-channel-attacks (SCA) and complexities of both on-chip and ambient environment, it is demanding to incorporate on-chip learnability into SCA anomaly detection. This will enable offline-trained models to adapt to the new power profiles of emerging SCA schemes, workloads, and varying environments. Existing SCA detection techniques often fall short in in-situ learning or pose excessive on-chip integration challenges due to resource and data demands. This paper presents a novel neuromorphic "compute-in-PUF" (CIPUF) architecture designed for SCA detection with on-chip learning capability and optimized area/energy/data overheads. We harness the PUF-based key generator as a hyperdimensional encoder, fostering few-shot learning capabilities. It showcases a state-of-the-art accuracy of 96% with offline training. While deployed on-chip, our architecture can adeptly re-calibrate its model at the introduction of unseen power profiles, and regain model accuracy by 45% with as few as 254 power trace samples during 0.45ms time frame. Meanwhile, compared with baseline design using separate PUF and learning modules, it achieves a area savings of 4.15X and energy savings of 12.8X. Nevertheless, it introduces a unique scalability advantages for both hardware key repository and learning accuracy for future technology.

The swift proliferation of edge intelligence and ubiquitous data generation have heightened privacy into a pressing societal need. State-of-the-art reversible privacy protection requires significant hardware resources at the edge with distinct architecture for sensors and security, leading to a rise in hardware overhead and expanded attack surfaces. To address these challenges, we propose a time-domain mixed-signal (TD-MS) circuit architecture facilitating in-situ privacy (ISP) with hardware-secured data reversibility. The proposed TD-MS ISP unites data acquisition, data conversion, key generation, and protection while providing authorized device-specific unclonable data recovery for forensic purposes. At the system level, we demonstrate the attack resilience and privacy-preserving computation performance by implementing a custom embedded system applied to real-world surveillance scenarios. At the circuit level, we showcase custom TD-MS circuits, evaluating their energy and area efficiency against a digital baseline implemented in 65nm technology. With full-stack SPICE simulations for both the baseline digital and proposed TD-MS circuits, we measured a$670\times$energy/frame savings against the embedded system,$3\times$area reduction and$3.2\times$energy TD-MS gains over digital.

With the ubiquitous IoT sensors and enormous real-time data generation, data privacy is becoming a critical societal concern. State-of-the-art privacy protection methods all demand significant hardware overhead due to computation-insensitive algorithms and divided sensor/security architecture. In this paper, we propose a generic time-domain circuit architecture that protects raw data by enabling a differentially-private compressed sensing (DP-CS) algorithm secured by physical unclonable functions (PUF). To address privacy concerns and hardware overhead at the same time, a robust unified PUF and time-domain mixed-signal (TD-MS) module are designed, where PUF enables private and secure entropy generation. To evaluate the proposed design against a digital baseline, we performed experiments based on synthesized circuits and SPICE simulation and measured a 2.9x area reduction and 3.2x energy gains. We also measured high-quality PUF generation with TD-MS circuit with a inter-die Hamming distance of 52% and a low intra-die Hamming distance of 2.8%. Furthermore, we performed attack and algorithm performance measurements demonstrating the proposed design preserves data privacy even under attack, and the machine learning performance has minimal degradation (within 2%) compared to the digital baseline.

Grasping an object in the presence of unpredictable disturbances and with no previous knowledge of the geometry and mass distribution of it represents a significant challenge in Robotics. Also, grasping an object with sufficient force to prevent slippage, whilst not damaging or deforming the shape of the object proves to be still an intricate challenge despite the existence of a huge body of literature on robotic grasping. This paper addresses this challenge by evaluating the performance of a Super Twisting Sliding Mode Control (STSMC) designed for preventing slippage meanwhile causing minimum deformation to the grasped object. The performance of the STSMC is evaluated against the one of a First Order Sliding Mode Controller (FOSMC). Both controllers use grip force and slip feedback to counteract the slippage. Force and slip detection are provided by low-cost, off-the-shelf sensors. Experimental results presented in this paper, show that, when grasping objects, both controllers can robustly overcome external nonlinear disturbances, along with inaccuracies in the system model, preventing slippage and minimising deformation of objects. However, from these results, we observe that the STSMC not only, as expected, eliminates the major drawback of the FOSMC, which is chattering, but also provides more consistent and robust response in terms of slippage and gripping force.