EDBT 2026 Demo / reviewers in the wild / expert
Ayas Kanta Swain
dblp:203/5655
· DBLP profile ↗
4ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0003-2124-1877ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | iClean: An Intelligent Industrial IoT Framework for Automatic Sustainable Air Quality MonitoringabstractAir pollution monitoring systems are essential for evaluating rural and industrial environmental quality for safeguarding public health. This study presents a comprehensive IoT-based framework that uses low-cost sensors and machine learning algorithms for real-time monitoring of various pollutants, including LPG, methane, CO, alcohol, PM2.5, PM10, temperature, and humidity. The system gathers sensor data from a gateway node, which is then processed using Support Vector Machines (SVM) and Random Forest Regression (RFR) models to predict pollutant concentrations. Our approach features innovative methodologies for data validation, anomaly detection, and predictive modeling, employing Root Mean Squared Error (RMSE) as the performance metric. The model achieved a remarkably low RMSE value of 0.022, significantly improving the accuracy and reliability of air quality assessments. Experimental results highlight the system's capability to capture complex environmental patterns and predict pollutant levels with high precision. This research intends air pollution monitoring from cost-effective Internet of Things (IoT) solutions and machine learning techniques. Additionally, the user interface is designed for mobile applications, offering real-time data access, alerts, and notifications, thereby enabling personalized environmental health management and targeted pollution control strategies in industrial areas. Lopamudra Samal, Aryan Samal, Kamala Kanta Mahapatra, Ayas Kanta Swain, Saraju P. Mohanty |
IEEE Trans. Sustain. Comput. | 4 |
| 2024 | PACAC: PYNQ Accelerated Cardiac Arrhythmia Classifier with secure transmission- A Deep Learning based ApproachabstractElectrocardiogram (ECG) signals are vital features to identify a healthy body; diagnosing cardiovascular diseases (CVDs) automatically using computer-aided tools has caught a significant attention in the current medical scenario. In recent times with the rapid growth of smart health-care system, IoT enabled edge devices make it possible for early diagnosis of diseases with resource constraint devices. PYNQ- a Python productivity on Xilinx platform, based hybrid CNN architecture has been proposed in this work for classifying arrhythmia in reference to AAMI (Association for the Advancement of Medical Instrumentation) EC57 standard. A comparative investigation is conducted on volume of trainable parameters of the architecture, and accuracy of ECG classification. A customized FPGA IP for the proposed hybrid 1-D CNN architecture has been generated using Vitis High Level Synthesis (HLS) tool that would be implemented on PYNQ-Z2 board. A lightweight cryptographic algorithm ASCON has been used in the proposed framework, wherein an authentication-based scheme for verifying an individual, via corresponding ECG signals is used, prior to sharing their data with various health-care entities furthermore enhancing information privacy. Soumyashree Mangaraj, Jaganath Prasad Mohanty, Samit Ari, Ayas Kanta Swain, Kamala Kanta Mahapatra |
ACM Great Lakes Symposium on VLSI | 4 |
| 2024 | Hardware Accelerated Quantized Hand Written Digit Recognition via High Level SynthesisabstractConvolutional Neural Networks (CNNs) have demonstrated remarkable success in image recognition tasks, but their deployment on resource-constrained devices remains challenging due to their computational complexity and memory requirements. This abstract presents an overview of hardware accelerator implementations for CNN-based image recognition, focusing on techniques to optimize performance, energy efficiency, and resource utilization. Hardware accelerators such as Field-Programmable Gate Arrays (FPGAs) offer parallel processing capabilities that can exploit the inherent parallelism in CNN computations. Design considerations include optimizing memory access patterns, and minimizing communication overhead between processing elements. Techniques such as pipelining, unrolling, quantization, and network compression are employed to reduce the computational and memory footprint of CNN models without significantly compromising accuracy. Hardware-software co-design methodologies enable seamless integration of CNN inference engines with host systems, facilitating real-time image recognition applications. The computational time of the proposed CNN is lower compared to that of the recent research works. Additionally, the proposed hardware design exhibits reduced memory, power consumption, and resource utilization as compared with recent literarture for MNIST digit recognition with 98.9% accuracy. Pawan Oraon, Soumyashree Mangaraj, Ayas Kanta Swain, Kamala Kanta Mahapatra |
ACM Great Lakes Symposium on VLSI | 3 |
| 2024 | Security-by-Design For Smart ElectronicsabstractThis article asserts that Artificial Intelligence (AI) has been the focus of research in recent years, and the Internet of Things devices powered by AI are proven to perform better than general purpose, but has given rise to a new set of challenges in privacy and security. The authors agree that a potential solution to improve security is through Hardware Assisted Security (HAS). Venkata P. Yanambaka, Ayas Kanta Swain, Saswat Kumar Ram, Saraju P. Mohanty |
ACM Great Lakes Symposium on VLSI | 2 |