In this paper a digital transmission unit for the forthcoming integrated services digital network (ISDN) is considered. Basic elements of such a unit are an adaptive echo canceller (EC) and an adaptive decision feedback equalizer (DFE). Each of these filters can be realized by a transversal filter structure or by a lookup table structure. An analysis and comparison of the behavior of these two structures is given, The combination of an EC and a DFE can also be realized by a single lookup table. It is shown that irrespective of the particular realization three different convergence phases can be distinguished, and that the overall convergence time is considerably longer then would be expected from the usual simple theory that ignores error propagation in the DFE. Two variants of a hardware realization of such a digital transmission unit are presented. They provide 144 kbit/s full-duplex transmission on the symmetrical cables of the existing local telephone network. A small transmission bandwidth is obtained by applying NRZ signaling. In the first circuit the EC and DFE are implemented by individual lookup tables, while in the second a combined table is used. Both circuits are to a large extent, implemented digitally. Due to the relatively low sampling frequency and the acceptably low power consumption they are very well suited for large scale integration with present day technology.

In this paper we present some tools that can be helpful in the design of adaptive digital filters operating with the so-called sign algorithm. Although theoretical results with respect to the convergence behavior of such filters are available, it may be hard to derive practical design criteria from them. We introduce a new type of design graph, which characterizes the convergence pretty well and which we call "the elephant's ear," due to its typical shape. We also consider some effects of non-Gaussian statistics of the received signal and show how the preceding analysis can be extended to include the effects of dithering. Finally, we pay attention to the digital word lengths required in a finite precision implementation. The subject of this paper is restricted to adaptive digital echo cancellers (EC), but the results can be generalized to include other adaptive filters like decision feedback equalizers (DFE) or combinations of EC and DFE.

The convergence of an adaptive echo canceller operating with the stochastic iteration algorithm in the presence of pseudo-noise data signals has been analyzed. This convergence can deviate appreciably from that with "random" data. An approximate expression for the convergence characteristic has been derived and verified by computer simulations.

This paper describes the application of a commercially available microprocessor (Intel 3000 or Signetics 3000) to a flexible data transmitter and data receiver for high-speed data modems. For the transmitter a quadrature modulation scheme is chosen; the receiver is based on phase-shift compensation techniques and coherent demodulation with an externally derived digital carrier. For the realization with the given microprocessor it has been necessary to adapt the way of executing the various operations (especially the multiplications for the digital filtering) to the available computational capabilities. The resulting microprocessor implementations are also suitable for application in the current medium-speed synchronous data transmission systems.

A digital filter is introduced consisting of a transversal part and a simple recursive network. The coefficients of the transversal part are equal to integer powers of two or zero; thus complicated multipliers are avoided and instead a simple routing circuit is used. Use of several types of the recursive network makes the filter applicable in different frequency ranges. The coefficients of the transversal part can be interpreted as differences of successive values of the impulse response of the filter. It is shown that this difference routing digital filter (DRDF) is especially suited for application in data transmission.

A frequency domain analysis of the digital generation of linearly modulated data waveforms is presented. It is shown that for any rational relation of line carrier frequency and digit frequency, digital data transmitters can be designed economically and adapted to large scale integration (LSI) techniques. Special attention is given to the elimination of digital multipliers throughout the system. The results are illustrated with an example of an all-digital vestigialsideband (VSB) transmitter, with a specially shaped output spectrum which facilitates carrier and clock recovery in the receiver.