This work presents a reference frequency and current generator circuit with high stability to temperature and process variations without requiring any post-fabrication trimming. The design serves as the reference generator in an active gate driver IC for Silicon Carbide transistors. It incorporates an 8MHz relaxation oscillator and a 12μA self-calibrating current reference. Both circuits share a parallel-connected discrete off-chip resistor and capacitor to eliminate the impact of on-chip process variations. A temperature stability of 45ppm/°C for the frequency and 54ppm/°C for the current is achieved by applying a closed-loop comparator error feedback as well as a resistor temperature compensation. The overall frequency and current standard deviation for process variations is 0.70% and 0.47%. The circuit is fabricated in a 0.18μm BCD technology.

This paper presents the design of a high-voltage (HV) single-inductor multiple-output (SIMO) fixed frequency DC-DC Buck converter for the power management unit of a Gate-Shaping digital gate driver for Silicon-Carbide power MOSFETs. Through shaping the switching waveform which drives the power MOSFET there are significant improvements regarding energy efficiency and electromagnetic compatibility achievable. Driving the gate of the power MOSFET the gate driver is provided with a galvanically isolated power supply of 20 V. Thus, the 0.4 W HV SIMO buck converter generates the internal 5 V and 1.8 V voltage rails required by the gate driver from the 20 V isolated power supply. It can provide up to 60 mA on each rail for analog and digital signal processing as well as driving the internal power MOSFETs. The design has been fabricated on an area of 0.6 mm2in a 0.18 µm HV BCD technology. In measurements it provides an average efficiency of 81.16 % over the whole operating range and a measured maximum efficiency of 87.44 %.

This work presents a novel zero-voltage-switching technique and demonstrates its feasibility in two exemplary DC-DC buck converters. The proposed system makes use of the nonlinearity of the reverse transfer capacitance to infer the voltage across the switch. The proposed method does not require additional expensive high-voltage components at the switch node, without resorting to bandwidth and voltage-limited high-voltage processes. The concept allows for full integration in low-cost, high-performance CMOS nodes, thereby enabling modern gate drivers with additional intelligent digital feature-sets to be used in HV environments. The technique is demonstrated to work using 650 V GaN and SiC switches across wide ranges of dead-times, regulating these from hundreds down to single nanoseconds.