EDBT 2026 Demo / reviewers in the wild / expert
Michael Hanhart
dblp:203/6554
· DBLP profile ↗
3ranked-venue papers
0as first author
3since 2021 · last 2024
0000-0002-8552-6006ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | A 28 nm 8.2-11.1 GHz Class-C Digitally Controlled Oscillator with 40 kHz Tuning ResolutionabstractThis paper proposes a class-C digitally controlled oscillator (DCO) using constantly-conducting NMOS biased switchable capacitor, aiming to optimize the off-state quality factor, reduce the off-state capacitance and improve the oscillator transient behavior. The DCO is fabricated in a 28 nm CMOS technology. With a unitary-weighted SC bank, the DCO shows an inherently monotonic tuning with a range of 8.2-11.1 GHz (30.1%), and a very fine tuning resolution of 40kHz. The class-C DCO achieves -115.5 dBc/Hz phase noise at 1 MHz offset from 10 GHz carrier frequency with 23 mW, resulting in a -182 dBc/Hz FoM and -191.5dBc/Hz FoMT. Lantao Wang, Johannes Bastl, Tim Lauber, Kenny Vohl, Jonas Meier, Andreas Köllmann, Ulrich Möhlmann, Michael Hanhart, Ralf Wunderlich, Stefan Heinen |
ISCAS | 8 |
| 2024 | A Trimming-Less External-RC Relaxation Oscillator With Self-Calibrating Current Reference for a SiC Active Gate Driver ApplicationabstractThis work presents a reference frequency and current generator circuit with high stability to temperature and process variations without requiring any post-fabrication trimming. The design serves as the reference generator in an active gate driver IC for Silicon Carbide transistors. It incorporates an 8MHz relaxation oscillator and a 12μA self-calibrating current reference. Both circuits share a parallel-connected discrete off-chip resistor and capacitor to eliminate the impact of on-chip process variations. A temperature stability of 45ppm/°C for the frequency and 54ppm/°C for the current is achieved by applying a closed-loop comparator error feedback as well as a resistor temperature compensation. The overall frequency and current standard deviation for process variations is 0.70% and 0.47%. The circuit is fabricated in a 0.18μm BCD technology. Erik Wehr, Tobias Zekorn, Michael Hanhart, Kenny Vohl, Léon Weihs, Ralf Wunderlich, Stefan Heinen |
ISCAS | 3 |
| 2022 | A 0.73-to-1.71 V Capacitor-less Low-Noise Low-Dropout Regulator in 28-nm CMOSabstractThis paper presents a low-noise low-dropout regulator (LNLDO) implemented in a 28 nm technology. The LNLDO features a two-stage architecture, using a low-pass filter with a very low cut-off frequency to separate the regulation loop and the noisy devices such as resistive divider and bandgap reference. Supplied by a 1.5 V-1.8 V input voltage, the LNLDO is able to provide a stable output voltage ranging from 0.73 V to 1.71 V, with a current supply ability from 0 to 35 mA. An on-chip capacitance enhancer is used to stabilize the regulation loop without an additional external capacitor. The RMS noise from 10 Hz to 100 kHz of the LNLDO is below 20μV. Lantao Wang, Running Guo, Johannes Bastl, Jonas Meier, Michael Hanhart, Tim Lauber, Alexander Meyer, Ralf Wunderlich, Stefan Heinen |
ISCAS | 5 |