Modern safety-critical systems often feature multi-core multi-SoC platforms and execute both periodic and sporadic workloads with real-time requirements. Periodic tasks benefit from a time-triggered (TT) approach, while sporadic events are best modeled by event-triggered (ET) tasks and scheduled using classical online mechanisms such as fixed-priority. Integrating TT and ET tasks in a multi-core environment has mainly been studied in fully partitioned solutions. However, for certain workloads, it may be beneficial to have a global scheduling approach for ET tasks. In this paper, we extend the current state-of-the-art in Response-Time Analysis (RTA) and Real-Time Calculus (RTC) to analyze the schedulability of sporadic ET tasks in a homogeneous multi-core TT system. We generalize previous promising results integrating TT and ET tasks using affine envelopes to homogeneous multi-core systems. While our method can be applied to any TT schedule generation mechanism, we also present a concrete schedule synthesis method based on a variant of the Least-Laxity First scheduling approach. We demonstrate the performance of our approach, in terms of both schedulability and runtime, through real-world and synthetic experiments inspired by real workloads. We note that our affine-envelope-based interference bound and the generalized burst limiting constraint (BLC) are also independent of the concrete TT synthesis algorithm and of the underlying timing analysis method (RTA or RTC). This modularity allows the framework to be combined with alternative schedulability analyses or TT schedule generation techniques, while preserving the demonstrated gains in schedulability and scalability for mixed TT and ET workloads on homogeneous multi-core platforms.

We introduce a new paradigm for synthesizing time-triggered schedules that guarantees the correct temporal behavior of time-triggered (TT) tasks and the schedulability of sporadic event-triggered (ET) tasks with arbitrary deadlines at design time. The approach first expresses a constraint for the TT task schedule in the form of a maximal affine envelope that ensures that as long as the schedule generation respects this envelope, all sporadic ET tasks meet their deadline. The second step consists of modeling this envelope as a burst limiting constraint (BLC) and building the schedule. The BLC constraint can be added to any existing TT schedule generation method as an additional constraint on the TT slot positioning. Here, we propose an efficient TT schedule generation method that integrates the BLC constraint via simulating a modified Least-Laxity-First (LLF) scheduler. We show via synthetic and real-world test cases that our novel method achieves better schedulability and a faster schedule generation for most use cases compared to other approaches inspired by, e.g., hierarchical scheduling. Moreover, we present an extension to our method that finds the most favorable schedule for TT tasks with respect to ET schedulability, thus increasing the probability that the system remains feasible when ET tasks are later added or changed.

In order to meet the requirements of critical applications, modern multi-core multi-SoC real-time systems must handle both periodic and sporadic events within specified deadlines. A two-level scheduling hierarchy that combines time-triggered and fixed-priority scheduling is effective for managing periodic time-triggered (TT) and sporadic event-triggered (ET) tasks, respectively. We introduce two polling-based approaches, called simple and advanced polling, for guaranteeing both TT and ET task deadlines within single core systems. We then propose an optimization heuristic for the task-to-core allocation problem based on genetic algorithms for fully partitioned multi-core systems that can be applied to both polling methods. We evaluate the schedulability and runtime performance of the polling approaches and investigate the effectiveness of the allocation heuristic using synthetic test cases based on real-world application characteristics. The results show that both polling approaches achieve high schedulability with low runtime, and the allocation heuristic can generate good solutions for fully partitioned systems. Furthermore, we show that the server design problem of the advanced polling approach can be integrated into the allocation heuristic to achieve better solutions in terms of schedulability and that our choice of the genetic algorithm has a good speedup when being parallelized.

Nowadays, most of cyber-physical systems in avionics, automotive or recent Industry 4.0 domains require networked communication for mixed-critical applications. Ethernet-based networks such as AFDX, TTEthernet or TSN are capable to support transmission of both safety-critical and non-critical flows. This paper focuses on the TTEthernet network compliant with the avionics ARINC 664-P7 standard supporting time-triggered communication (TT) together with rate-constrained (RC) and best-effort (BE) traffic. Due to a global synchronization, TT communication with low latency and minimal jitter is ensured with static schedules computed offline. For event-triggered RC flows, bounded jitter at the source and end-to-end latency are guaranteed with worst-case analysis methods. With the increasing demands of applications, flows with Quality of Service (QoS) requirements such as video or audio may be transmitted as BE flows. However, on current configurations, no guarantees are offered to BE flows. In this paper, we aim at increasing the maximum RC utilization and improving the QoS of BE flows to allow the transmission of video or audio traffic with low jitter and end-to-end delay requirements. For this, we focus on the scheduling mechanisms and propose a scheduling approach based on a static slotted table that is applied at end systems. This table integrates the TT schedules usually obtained with Satisfiability Modulo Theories (SMT) approaches and establishes offsets of RC flows that reduce the end-to-end delay of BE flows. Several strategies for offset computations are proposed based on the distribution of flows locally at end system or globally at switch. We show that local strategies perform better than the global ones to reduce end-to-end delay of BE flows.

TTEthernet is an Ethernet-based synchronized network technology compliant with the AFDX standard. It supports safety-critical applications by defining different traffic classes: Time-Triggered (TT), Rate-Constrained (RC), and Best-Effort traffic. The synchronization is managed through the AS6802 protocol, which defines so-called Protocol Control Frames (PCFs) to synchronize the local clock of each device. In this paper, we analyze the synchronization protocol to assess the impact of the PCFs on TT and RC traffic. We propose a method to decrease the impact of PCFs on TT and a new Network Calculus model to compute RC delay bounds with the influence of both PCF and TT traffic. We finish with a performance evaluation to i) assess the impact of PCFs, ii) show the benefits of our method in terms of reducing the impact of PCFs on TT traffic and iii) prove the necessity of taking the PCF traffic into account to compute correct RC worst-case delays and provide a safe system.

In mixed-criticality Ethernet-based time-triggered networks, like TTEthernet, time-triggered communication (TT) coexists with rate-constrained (RC) and best-effort (BE) traffic. A global communication scheme, i.e., a schedule, establishes contention-free transmission times for TT flows ensuring guaranteed low latency and minimal jitter. Current approaches use Satisfiability Modulo Theories (SMT) to formulate the scheduling constraints and solve the resulting problem. However, these approaches do not take into consideration the impact of the TT schedule on RC traffic. Hence, the resulting TT schedule may cause the worst-case latency requirements of RC traffic not to be fulfilled anymore.In this paper, we present a novel method for including an RC analysis in state-of-the-art SMT-based schedule synthesis algorithms via a feedback loop in order to maintain the optimality properties of the SMT-based approaches while also being able to improve the RC traffic delays. Our method is designed in such a way that it can be readily integrated into existing SMT- or MiP-based solutions. We evaluate our approach using variants derived from a realistic use-case and present methods to further improve the efficiency of our feedback-based approach.

We define a novel core network router scheduling architecture to carry and isolate time constrained and elastic traffic flows from best-effort traffic. To date, one possible solution has been to implement a core DiffServ network with standard fair queuing and scheduling mechanisms as proposed in the well-known “A Differentiated Services Code Point (DSCP) for Capacity-Admitted Traffic” from RFC5865. This architecture is one of the most selected solutions by internet service provider for access networks (e.g. Customer-Premises Equipment or satellite PEP). In this study, we argue that the proposed standard implementation does not allow to efficiently quantify the reserved capacity for the AF class. By using a novel credit based shaper mechanism called Burst Limiting Shaper, we show that we can provide the same isolation for the time constrained EF class while better quantifying the part allocated to the AF class.