EDBT 2026 Demo / reviewers in the wild / expert
Teguh Hofstee
dblp:204/0044
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2020
0000-0002-1808-6282ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1Graphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 61% Reconfigurable computing and FPGAs · 30% Hardware accelerators and domain-specific architectures · 9% | |
| Computer graphics and multimedia
1 paper |
Rendering · 100% | |
| Software engineering, system software, and programming languages
1 paper |
Requirements engineering and software design · 100% |
Topics — the 5 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Reconfigurable computing and FPGAs
coarse-grained reconfigurable architecture |
0.4 | 1 | 2020 | Creating an Agile Hardware Design Flow · DAC 2020 |
Electronic design automation
hardware/software co-design |
0.4 | 1 | 2020 | Creating an Agile Hardware Design Flow · DAC 2020 |
Rendering
real-time rendering |
0.3 | 1 | 2017 | Shader components: modular and high performance shader development · ACM Trans. Graph. 2017 |
Rendering › shader programming
shading languages |
0.3 | 1 | 2017 | Shader components: modular and high performance shader development · ACM Trans. Graph. 2017 |
Requirements engineering and software design › modularity
modularity mechanisms |
0.1 | 1 | 2017 | Shader components: modular and high performance shader development · ACM Trans. Graph. 2017 |
Methods — techniques the papers use, named apart from their topics
static specialization · 0.6shader components · 0.6hardware generator · 0.4domain-specific language · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2020 | Creating an Agile Hardware Design FlowabstractAlthough an agile approach is standard for software design, how to properly adapt this method to hardware is still an open question. This work addresses this question while building a system on chip (SoC) with specialized accelerators. Rather than using a traditional waterfall design flow, which starts by studying the application to be accelerated, we begin by constructing a complete flow from an application expressed in a high-level domain-specific language (DSL), in our case Halide, to a generic coarse-grained reconfigurable array (CGRA). As our under-standing of the application grows, the CGRA design evolves, and we have developed a suite of tools that tune application code, the compiler, and the CGRA to increase the efficiency of the resulting implementation. To meet our continued need to update parts of the system while maintaining the end-to-end flow, we have created DSL-based hardware generators that not only provide the Verilog needed for the implementation of the CGRA, but also create the collateral that the compiler/mapper/place and route system needs to configure its operation. This work provides a systematic approach for desiging and evolving high-performance and energy-efficient hardware-software systems for any application domain. Rick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas 0003, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang |
DAC | 11 |
| 2017 | Shader components: modular and high performance shader developmentabstractModern game engines seek to balance the conflicting goals of high rendering performance and productive software development. To improve CPU performance, the most recent generation of real-time graphics APIs provide new primitives for performing efficient batch updates to shader parameters. However, modern game engines featuring large shader codebases have struggled to take advantage of these benefits. The problem is that even though shader parameters can be organized into efficient modules bound to the pipeline at various frequencies, modern shading languages lack corresponding primitives to organize shader logic (requiring these parameters) into modules as well. The result is that complex shaders are typically compiled to use a monolithic block of parameters, defeating the design, and performance benefits, of the new parameter binding API. In this paper we propose to resolve this mismatch by introducing shader components , a first-class unit of modularity in a shader program that encapsulates a unit of shader logic and the parameters that must be bound when that logic is in use. We show that by building sophisticated shaders out of components, we can retain essential aspects of performance (static specialization of the shader logic in use and efficient update of parameters at component granularity) while maintaining the modular shader code structure that is desirable in today's high-end game engines. Yong He 0013, Theresa Foley, Teguh Hofstee, Haomin Long, Kayvon Fatahalian |
ACM Trans. Graph. | 3 |