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Valerio Bruschi

dblp:204/5581 · DBLP profile ↗
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5ranked-venue papers
2as first author
1since 2021 · last 2021
0000-0003-3563-6028ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Computer networks · 4 · 2 first-author · 1 since 2021Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer networks
3 papers
Software-defined and programmable networks · 34% Network measurement and analytics · 33% Internet architecture and protocols · 29%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Software-defined and programmable networks
programmable data plane
0.522020
FlowBlaze: Stateful Packet Processing in Hardware · NSDI 2019
DISCOvering the heavy hitters with disaggregated sketches · CoNEXT 2020
Network measurement and analytics
flow monitoring
0.412020
DISCOvering the heavy hitters with disaggregated sketches · CoNEXT 2020
Network measurement and analytics
heavy hitter detection
0.412020
DISCOvering the heavy hitters with disaggregated sketches · CoNEXT 2020
Internet architecture and protocols › packet processing
packet classification
0.412019
TupleMerge: Fast Software Packet Processing for Online Packet Classification · IEEE/ACM Trans. Netw. 2019
Software-defined and programmable networks › programmable data plane
stateful packet processing
0.412019
FlowBlaze: Stateful Packet Processing in Hardware · NSDI 2019
Internet architecture and protocols › packet processing › packet classification
tuple space search
0.412019
TupleMerge: Fast Software Packet Processing for Online Packet Classification · IEEE/ACM Trans. Netw. 2019
Routing and switching › router architecture
software router
0.112019
TupleMerge: Fast Software Packet Processing for Online Packet Classification · IEEE/ACM Trans. Netw. 2019
Hardware accelerators and domain-specific architectures
network accelerator
0.112019
FlowBlaze: Stateful Packet Processing in Hardware · NSDI 2019

Methods — techniques the papers use, named apart from their topics

stateful processing · 0.8FPGA-based packet processing · 0.8disaggregated sketches · 0.4tuple space search · 0.4hash table · 0.4
YearPublicationVenuePosition
2021 FlowFight: High performance-low memory top-k spreader detection
Valerio Bruschi, Salvatore Pontarelli, Jerome Tollet, David Barach, Giuseppe Bianchi 0001
Comput. Networks1
2020 DISCOvering the heavy hitters with disaggregated sketches
abstract
We propose DISCO - a lightweight approach to flow monitoring in the data plane. The idea is to disaggregate the computation of a single (logically) centralized sketch into multiple small "sketch fragments" that are distributed across the flows' paths. This allows use less resources at switches without trading on telemetry capabilities.
Valerio Bruschi, Ran Ben-Basat, Zaoxing Liu, Gianni Antichi, Giuseppe Bianchi 0001, Michael Mitzenmacher
CoNEXT1
2019 FlowBlaze: Stateful Packet Processing in Hardware
Salvatore Pontarelli, Roberto Bifulco, Marco Bonola, Carmelo Cascone, M. Spaziani Brunella, Valerio Bruschi, Davide Sanvito, Giuseppe Siracusano, Antonio Capone, Michio Honda, Felipe Huici
NSDI6
2019 TupleMerge: Fast Software Packet Processing for Online Packet Classification
abstract
Packet classification is an important part of many networking devices, such as routers and firewalls. Software-defined networking (SDN) heavily relies on online packet classification which must efficiently process two different streams: incoming packets to classify and rules to update. This rules out many offline packet classification algorithms that do not support fast updates. We propose a novel online classification algorithm, TupleMerge (TM), derived from tuple space search (TSS), the packet classifier used by Open vSwitch (OVS). TM improves upon TSS by combining hash tables which contain rules with similar characteristics. This greatly reduces classification time preserving similar performance in updates. We validate the effectiveness of TM using both simulation and deployment in a full-fledged software router, specifically within the vector packet processor (VPP). In our simulation results, which focus solely on the efficiency of the classification algorithm, we demonstrate that TM outperforms all other state of the art methods, including TSS, PartitionSort (PS), and SAX-PAC. For example, TM is 34% faster at classifying packets and 30% faster at updating rules than PS. We then experimentally evaluate TM deployed within the VPP framework comparing TM against linear search and TSS, and also against TSS within the OVS framework. This validation of deployed implementations is important as SDN frameworks have several optimizations such as caches that may minimize the influence of a classification algorithm. Our experimental results clearly validate the effectiveness of TM. VPP TM classifies packets nearly two orders of magnitude faster than VPP TSS and at least one order of magnitude faster than OVS TSS.
James Daly, Valerio Bruschi, Leonardo Linguaglossa, Salvatore Pontarelli, Dario Rossi 0001, Jerome Tollet, Eric Torng, Andrew Yourtchenko
IEEE/ACM Trans. Netw.2
2017 On offloading programmable SDN controller tasks to the embedded microcontroller of stateful SDN dataplanes
abstract
This paper presents a method to implement complex tasks into stateful SDN programmable dataplanes. In particular, the presented method proposes to use the internal microcontroller typically used to configure the programmable dataplane also to perform some complex operations that do not require to be executed on each packet. These operations can be executed on a set of data gathered by the dataplane and processed in a time scale that is much higher than the time window of a packet, but is much less than time scale needed for an external SDN controller. Moreover, the use of the configuration microcontroller instead of an external SDN controller to avoid the exchange of data on the control links permits a fine grain tuning of the operations to perform from the timing point of view (precise timestamping, low latency etc.). A set of measurements showing the feasibility of the method are presented, and a simple use case is described to show the effectiveness of this method to enhance the capability of stateful programmable dataplanes.
Salvatore Pontarelli, Valerio Bruschi, Marco Bonola, Giuseppe Bianchi 0001
NetSoft2