The large capacity and energy-efficient shared Last Level Caches play a vital role in improving system performance with a relatively low power consumption in the modern processors. Unfortunately, this highly utilized shared resource often turns out to be a primary target for some malicious attackers. In particular, depending on the inherent timing difference between a cache hit and a miss, attackers in the form of malicious applications running on different cores can exchange information in an indirect manner, creating a so-called covert channel. Although many such attacks and their countermeasures have been proposed in the literature, the possibility of a newer variant cannot be underestimated. This article presents a novel covert channel attack that exploits the vulnerabilities in the existing buffer-based defence mechanism against Last Level Cache (LLC) timing attacks. Building upon the Flush+earlyReload (F+eR) attack mechanism, we demonstrate a new attack that targets the fixed buffer size limitations in the current defence implementation against F+eR. Our attack, termed “Buffer Saturation Attack” (BSA), exploits the predictability of buffer capacity and the already in-place First In First Out (FIFO) eviction policy to create reliable covert channels for transmission of confidential information between malicious applications called spy and trojan . Furthermore, we propose a defence mechanism called Request Capping (ReCap) that identifies and subsequently prevents the malicious activities by limiting the number of consecutive requests from each individual core. Through experimental analysis, we show that BSA can achieve high transmission accuracy by strategically overwhelming the buffer with carefully timed requests.

With the rising demands for high capacity memory and poor scalability of the existing DRAM-based main memories, the emerging Non-volatile memories captures higher attention due to their high density and low leakage power consumption. However, the possible consideration of such memories as alternatives of DRAM is largely hindered by their intrinsic drawbacks like high write latency, high write energy and low write endurance. In this article, we propose an integrated solution by combining the effect of compression and encoding assisted block placement to improve lifetime of NVMs. We have developed a compression technique called LUT_Comp by exploiting the word-level redundancy present in the words of the incoming cache blocks to NVM. LUT_Comp remains effective in reducing bit-flips in NVMs by offering a balance in compression ratio and coverage (Cov). Additionally, we also propose an encoding based block placement policy that places the compressed blocks in the appropriate half within the memory. The integrated approach of compression and block placement termed AmLuCEP offers a uniform bit-flips distribution while further reducing bit-flips in NVM. Experimental results show that AmLuCEP reduces bit-flips by 54%, 42%, 37%, 21%; energy consumption by 41%, 28%, 24%, 13%; and improves lifetime by 57%, 40%, 38%, 21% over baseline and the existing techniques READ [ 38 ], COEF [ 39 ] and SELEC [ 13 ], respectively.

In this paper, we propose a technique called CoSeP that combines the effect of compression and the content of the compressed blocks to reduce bit-flips in the encrypted PCM-based main memories. The blocks are compressed using the technique (out of FPC, BDI, and COMF) that offers minimum block size when the sizes of the two smallest compressed blocks are non-similar. However, for compressed blocks of similar sizes, the block is compressed using the technique that encounters minimum bit-flips, which reduces bit-flips further. Experimental results show that our technique gives a substantial reduction in bit-flips and improvements in lifetime compared to baseline and state-of-the-art techniques.

Emerging Non-volatile memories are considered as potential candidates for replacing traditional DRAM in main memory. However, downsides like long write latency, high write energy, and low write endurance make their direct adoption in the memory hierarchy challenging. Approaches that reduce the number of bits written are beneficial to overcome such drawbacks.

Emerging Non-Volatile memories such as Phase Change Memory (PCM) and Resistive RAM are projected as potential replacements of the traditional DRAM-based main memories. However, limited write endurance and high write energy limit their chances of adoption as a mainstream main memory standard. Therefore, developing solutions that enhance the lifetime of these memories while offering a decent system performance has a great impact in building future large capacity and energy-efficient main memories. In this paper, we propose a word-level compression scheme called COMF to reduce bitflips in PCMs by removing the most repeated words from the cache blocks before writing into memory. COMF is augmented with an adaptive granularity based encoding technique to form COFAE, which reduces the bitflips to a further extent. We also propose SWEL-COFAE, which is an intra-line stride-based wear leveling technique to improve lifetime by balancing the bitflip pressure within the cells of the memory lines. Experimental results show that the proposed technique improves lifetime by 103% and reduces bitflips and energy by 60% and 59% respectively over baseline

Emerging nonvolatile memories (NVMs) are considered as potential replacements of the traditional DRAM-based main memories. However, the nonvolatility feature of the NVMs may lead to the stealing of sensitive data stored in NVMs due to their prolonged data retention. Memory encryption turns out to be a viable option to provide data security. However, the existing encryption techniques, on account of the diffusion property, increase the number of bit-flips in the NVM cells, thus leading to their early wear out. Therefore, security and lifetime issues of the NVMs are difficult to go hand in hand. In this article, we identify words that are repeated in several memory blocks and term them as popular words. The proposal is to avoid the encryption of the popular words by maintaining them in a reference table. In our proposal, Pop-Crypt, every block to be written to the memory gets partially encrypted in which the popular words are replaced with pointers to the reference table, and other words get encrypted. The partially encrypted blocks (PEBs) reduce the number of bit-flips in PCM, thereby improving its lifetime significantly. Experimental results show that Pop-Crypt considerably improves lifetime, energy consumption, and system performance over baseline and a state-of-the-art technique.

Emerging Non-Volatile memories such as Phase Change Memory (PCM) and Resistive RAM are projected as potential replacements of the traditional DRAM-based main memories. However, limited write endurance and high write energy limit their chances of adoption as a mainstream main memory standard.

Hybrid main memories comprising DRAM and Non-volatile memories (NVM) are projected as potential replacements of the traditional DRAM-based memories. However, traditional cache management policies designed for improving the hit rate lack awareness of the comparative latency of read-write for NVM blocks where the write latency is more than the read latency. Therefore, developing cache management techniques that reduce costly write-backs of the NVM blocks, yet maintain a fair hit rate in the cache, is of paramount importance. We propose two techniques based on the use of a small victim cache associated with the last-level cache that helps in retaining on the chip critical DRAM and NVM blocks. Victim cache being a scarce resource, we intend to keep only performance-critical blocks in the victim cache by exploiting the idea of reuse distance. The first technique, Victim Cache Replacement Policy, works on the replacement policy of the victim cache by preferential eviction of DRAM blocks over NVM blocks. However, the second technique, Prioritized Partitioning of victim cache, logically partitions the victim cache, giving a smaller share to the DRAM blocks and a relatively larger share to the NVM blocks. Experimental evaluation on full-system simulator shows significant improvement in system performance and reduction in the number of write-backs to the NVM partition of the main memory compared to the baseline and existing technique. Additionally, NVM reads and DRAM miss rate are also improved, leading to further performance enhancement.