EDBT 2026 Demo / reviewers in the wild / expert
Gyutae Kim
dblp:204/9681
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2026
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Cloud and datacenter computing · 61% Processor architecture and microarchitecture · 30% Performance modeling and evaluation · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Cloud and datacenter computing › cluster resource management and scheduling
cluster resource management |
1.0 | 1 | 2026 | SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters · HPCA 2026 |
Cloud and datacenter computing
job scheduling |
1.0 | 1 | 2026 | SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters · HPCA 2026 |
Processor architecture and microarchitecture › multithreading
simultaneous multithreading |
1.0 | 1 | 2026 | SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters · HPCA 2026 |
Performance modeling and evaluation › performance model construction › memory system performance modeling
contention modeling |
0.3 | 1 | 2026 | SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters · HPCA 2026 |
Methods — techniques the papers use, named apart from their topics
microbenchmarking · 1.0contention modeling · 1.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in DatacentersabstractSimultaneous multithreading (SMT) is widely used in modern x86 processors to improve core utilization by sharing hardware resources between co-located threads. However, such resource sharing often leads to severe performance interference, making efficient workload co-scheduling difficult, especially given the complexity and diversity of modern x86 CPUs. Our analysis reveals that SMT-aware workload scheduling can significantly improve system throughput and reduce tail latency for datacenter workloads, but identifying optimal thread combinations is challenging due to the lack of visibility into platform-specific resource sharing behaviors. In this paper, we present SMTcheck, a lightweight, accurate, and platformindependent methodology for predicting SMT interference for diverse x86 processors. SMTcheck uses carefully designed code snippets (Diags) to extract hidden microarchitectural features of performance-critical shared resources. With these extracted features, SMTcheck builds per-resource microbenchmarks (Injectors) to apply pinpoint pressure to specific target resources in order to capture workload-specific contention characteristics. SMTcheck then constructs a hardware-aware contention model to predict performance interference between arbitrary workload pairs without requiring exhaustive profiling. We evaluate SMTcheck on six x86 desktop processors and five x86 server processors from Intel and AMD across different generations and show that it achieves high prediction accuracy by up to 95.5 % (94.6 % on average). We further demonstrate its effectiveness by implementing a contention-aware scheduler in the Linux kernel. Compared to the default Linux scheduler, our contention-aware scheduler significantly reduces tail latency for latency-critical workloads (e.g., database, key-value store) by up to 36.09 %, and improves the overall system throughput by up to$1.072 \times$. Finally, using real-world cluster traces from Alibaba and Google, we demonstrate that SMTcheck incurs negligible profiling overheads ($\approx 0.113 \%$), making it practical for deployment in productionscale datacenter environments. Jinhyeok Oh, Gyutae Kim, Youngsok Kim, Jae-Hyun Hwang, Joonsung Kim 0001 |
HPCA | 4 |