This paper presents a full hardware implementation of a magnetic tunnel junction based stochastic tunable bitstream generator. It provides highly accurate control of the switching probability, while showing important robustness to process and temperature variations. We propose a new architecture of sensing scheme based on the pre-charged sense amplifier approach that uses an asynchronous digital module to control the internal signals of the sense amplifier with the purpose of improving the reliability against the timing hazards and reducing the power consumption by detecting the end of the reading to stop the required static currents. The circuit also features a digital feedback loop that analyzes the output bitstream and adapt the current in such a way that the bitstream encodes precisely the required probability. This circuit features an important bit generation rate at a low energy cost. Based on an exhaustive characterization of the circuit, we provide a behavioral description in Verilog, with timing and power files to be integrated as a standard cell in the digital design flow for application level evaluation of the performance. Thus, we also provide a design and evaluation flow from device to digital level of abstraction.

The state-of-the-art solid-state drives (SSDs) now heterogeneously integrate NAND Flash and dynamic random access memories (DRAMs) to partially hide the limitation of the nonvolatile memory technology. However, due to the increased request for storage density coupled with performance that positions the storage tier closer to the latency of the processing elements, NAND Flash are becoming a serious bottleneck. DRAM as well are a limitation in the SSD reliability due to their vulnerability to the power loss events. Several emerging memory technologies are candidate to replace them, namely the storage class memories. Phase change memories and magnetic memories fall into this category. In this work, we review both technologies from the perspective of their possible application in future disk drives, opening up new computation paradigms as well as improving the storage characteristics in terms of latency and reliability.

The recent advent of spin transfer torque (STT) has shed a new light on MRAM with the promises of much improved performances and greater scalability to very advanced technology nodes. As a result, MRAM is now viewed as a credible solution for stand-alone and embedded applications where the combination of non-volatility, speed and endurance is key. Whereas the technology is nearing maturity for DRAM replacement, with the exception of process scaling to sub-20nm which remains a challenge, circuit designers are now actively looking at SoCs where MRAM could bring in better performance and lower power consumption in data intensive applications as well as instant-on capability in mobile applications. In this paper we present a review of the MRAM technology and a methodology for ASIC design using a custom full digital hybrid CMOS/Magnetic Process Design Kit. We finish by a few examples showing that magnetic memories can be efficiently integrated in logic designs, for both safety and low power purposes.