The lithography process inherently introduces device-to-device variation in the fabrication of resistive random-access memory (RRAM) array, introducing electrical mismatch and limiting the practical applications of RRAM-based analog computing circuits. In this work, we propose a lithography model-aware layout synthesis framework to minimize the proximity effect in the lithography process, thus reducing the electrical mismatch amongst these devices for analog computing applications. A dummy RRAM cell insertion technique is proposed to reduce the geometrical mismatch among RRAM cells, and a bi-objective alternate optimization method is proposed to efficiently optimize the geometric parameters and the structure of RRAM layouts. In addition, an approximation method for evaluating the quality of the RRAM array layout is proposed to reduce the runtime of synthesis. The experimental results show that our proposed framework significantly reduces the deviation between printed and expected patterns.

Compact models of transistors are essential for simulating and optimizing circuits with the use of SPICE simulation tool. Parameter extraction, which is calibrating these models, is essential to ensure their alignment with measured or simulated data. However, conventional parameter extraction methods are generally iterative and experience-dependent, requiring significant time and effort from modeling engineers. Moreover, as semiconductor devices and compact models become increasingly advanced, the need for a tailored extraction process for each model has become increasingly inefficient. To address the above challenges, this work proposes an agile transistor compact modeling framework, ATMAD. The proposed framework takes a compact model file and a set of electrical characteristic data as inputs, producing a calibrated model with minimal human intervention. ATMAD automatically retrieves the equations in the compact model and converts them into computational flow graphs, thus supporting different compact models with a generalized process. A graph unlooping technique is proposed to support automatic differentiation for compact models with implicit functions (e.g., series resistance and surface potential solving). Based on the computational flow graph, ATMAD adopts automatic differentiation technique to achieve automatic and parallel optimization of model parameters. The proposed ATMAD framework is validated on commonly-used compact models in academia and industry, showing its effectiveness for compact modeling for both I-V and C-V characteristics.

Advanced semiconductor lithography faces significant challenges as feature sizes continue to shrink, necessitating effective Multiple Patterning Layout Decomposition (MPLD) algorithms. Existing MPLD algorithms are inefficient or cannot support stitch insertion to achieve finer-grained optimal decom-position. This paper introduces an end-to-end GNN-based frame-work that not only achieves high-quality solutions quickly but also applies to layouts with stitches. Our framework treats layouts as heterogeneous graphs and performs inference through a message-passing mechanism. We deliver ultra-competitive, near-optimal solutions that are 10x faster than the exact algorithm (e.g., integer linear programming) and 3x faster than approximate algorithms (e.g., exact-cover, semi-definite programming).

Healthcare Education and Labeling for Cardiopulmonary Sounds, HEALSound, is an interactive platform designed to enhance the identification and labeling of adventitious cardiopulmonary sounds through gamification. HEALSound enables users, particularly medical professionals, to engage in exercises that improve their knowledge of abnormal heart and lung sounds while simultaneously contributing to the labeling of raw audio data. By incorporating real-time feedback and progress tracking, the app promotes continuous learning and provides a valuable crowdsourced resource for building high-quality labeled datasets over time. This dual-purpose platform not only aids in medical education but also contributes to the advancement of machine learning models for sound classification in healthcare. The system demonstrates a new potential for significant impact in educational and clinical environments by seamlessly integrating learning with data collection, ensuring scalability and the continuous improvement of cardiopulmonary sound databases.

Advances in digital stethoscopes and wearable health sensors now support real-time cardiopulmonary monitoring and AI-driven diagnostic tools. However, the extensive manual labeling required for large datasets of respiratory sounds presents a significant barrier, traditionally dependent on expert input. To address this, we introduce HEALSound, a mobile application designed to blend educational training with crowdsourced data labeling. By engaging users in interactive auscultation exercises and providing immediate feedback, HEALSound promotes skill development while generating high-quality labeled data through weighted consensus methods. Experimental results highlight the app’s dual effectiveness: enhancing diagnostic learning for users and accelerating the development of machine-learning models through enriched datasets, thus addressing critical challenges in AI-based health diagnostics.

Modeling lithography using machine learning is extremely data-intensive. Due to intellectual property privacy concerns and potential malicious attacks, design houses and foundries are unwilling to share their designs directly. To address the aforementioned concerns, we have proposed a personalized federated learning-based framework (pFed-Litho) to perform end-to-end lithography simulation. This framework incorporates a cross-level local training algorithm along with an integrated optimization method to generate personalized and local models, which overcome the generalization problem and slow convergence and oscillatory behavior in its loss function, respectively. The experimental results show that our pFed-Litho framework achieves up to 14.07% higher accuracy with reduced oscillatory behavior in the loss curve compared to the state-of-the-art works. Even with a dataset reduced by$100\times $, our framework maintains a stable accuracy of over 91%, representing a 50% increase compared to the U-Net model.

Data-retention flip-flops (DR-FFs) efficiently maintain data during sleep mode, and retain state during transitions between active and sleep mode. This brief proposes an ultralow power DR-FF design with an improved autonomous data-retention (ADR) latch operating with a supply voltage range down to near/subthreshold, achieving a sleep mode leakage power of 12.2 pW,$1.4\times $–$3.8\times $less than the prior CMOS DR-FFs. Our proposed DR-FFs consume the lowest active mode switching efficiency of 36.5 fJ/step,$1.2\times $–$4\times $less than the prior works, and a comparable transition efficiency of 1.9 fJ/step. Furthermore, our proposed DR-FFs require minimal control signals, logic gates, and switches, significantly reducing design complexity, and avoiding the drawbacks of nonvolatile data retention FFs (NV-FFs).

This work introduces an innovative wearable health-care system that offers personalized cardiopulmonary monitoring by continuously capturing a variety of physiological signals. Users can engage with the system to view their own data in real-time, thereby gaining a nuanced understanding of its multi-modal sensing capabilities and the potential for remote health monitoring.

Continuous physiological sound monitoring is crucial for the prevention, diagnosis, and treatment of various diseases like cardiopulmonary and gastrointestinal conditions. Wearable healthcare sensors have emerged as a potent solution, streamlining the capture, storage, transmission, and analysis of individualized physiological sounds. However, challenges exist including large data volumes, limited hardware computational capabilities, and constrained transmission bit rates. To address these issues, we propose a physiological sound compression system using compressive sensing with self-adaptive compression ratio across sound types to implement physiological sound compression and Optimized Discrete Cosine Transform (ODCT) reconstruction to reduce loss in effective bands. Evaluated on SPRSound and PhysioNet 2016, our approach attains correlation coefficients of 0.863 and 0.883 for respiratory and cardiac sounds, with -3.14 dB and -1.84 dB signal-to-noise ratio loss at 3.5 and 3.0 compression ratios. Implemented on a custom healthcare sensor, our approach optimizes bit rate to 1.73× and power consumption to 0.82× compared to the uncompressed system.

The fast-growing development in wearable electronic devices leads to high demand for small-volume, lightweight, and high-efficiency DC-DC power converters, particularly switched capacitor (SC) DC-DC converters. In this paper, we propose a synthesis framework of step-down SC DC-DC power converters to obtain an optimum converter topology under the design constraints of the conversion ratio and a minimum number of capacitors. The proposed rule-based clustering reduction techniques have reduced the search space and sped up the conversion ratio analysis. In the case study of 8:1 converter synthesis, the run-time for conversion ratio analysis is reduced by 1.26$\boldsymbol{\times}$$\boldsymbol{10^6}$. The proposed efficiency optimization method has improved the peak efficiencies of the cascaded 2:1 converter and Fibonacci converter by 4.7% and 12.8%. The proposed framework has identified new topologies and variants of conventional topologies. The variant of cascaded 2:1 converter shows an improvement of 8.2% on peak efficiency.

Conventional physics-based memristor device modeling methods highly rely on human expertise, which results in a long development period. To address the aforementioned challenges, we propose a new generalized memristor (GEM) device modeling framework based on the artificial neural network (ANN) technique, which has a minimum dependency on the underlying physics, resulting in a fast turn-around development time for customized memristor devices. GEM framework models the switching and conducting behaviors of the memristor devices separately, avoiding the signal-dependence issue in the prior time-series data modeling method. The result of the GEM framework is a compact model that supports general-purpose circuit simulators. Experimental results show that our compact model achieves a ratio of root-mean-square error to peak-to-peak (RMSE/PP) of 3.6% compared to the physics-based device model. Performance analysis of memristor-based logic and memristor crossbar circuits are conducted to demonstrate the effectiveness of our proposed GEM framework for the design and analysis of memristor-based circuits.

Malicious manipulation of very large-scale integration physical-layout design is a serious problem in modern integrated circuit design. The physical-layout design database requires a highly compressed secured storage medium. In this article, we propose a secured compressive asymmetrical convolutional auto-encoder (ACAE) machine learning framework, CompressKey, which performs layout compression and encryption simultaneously. It utilizes geometric features to eliminate redundancies in layout patterns. We propose a “Divide and Merge” technique to partition each layer into smaller sizes of unique patterns to address the inconsistency of layout pattern complexity. We also propose “Matrix Expansion” and “Matrix Reduction” techniques on the matrix-based pattern to achieve secured “near lossless” compression on the layouts. We have evaluated CompressKey on 14/28/32 nm open-source ICCAD contest databases and achieved a secured compression ratio of 4.54 with encryption features outperforming$1.22\times $–$1.59\times $compared to the state-of-the-art techniques.

Performing chemical mechanical polishing (CMP) modeling for physical verification on an integrated circuit (IC) chip is vital to minimize its manufacturing yield loss. Traditional CMP models calculate post-CMP topography height of the IC’s layout based on physical principles and empirical experiments, which is computationally costly and time-consuming. In this work, we propose a CmpCNN framework based on convolutional neural networks (CNNs) with a transfer learning method to accelerate the CMP modeling process. It utilizes a multi-input strategy by feeding the binary image of layout and its density into our CNN-based model to extract features more efficiently. The transfer learning method is adopted to different CMP process parameters and different categories of circuits to further improve its prediction accuracy and convergence speed. Experimental results show that our CmpCNN framework achieves a competitive root mean square error ( RMSE ) of 2.7733Å with 1.89× reduction compared to the prior work, and a 57× speedup compared to the commercial CMP simulation tool.

The design and verification of memristor crossbar circuits and systems demand computationally efficient models. The conventional device-level memristor model with a circuit simulator such as simulation program with integrated circuit emphasis (SPICE) to solve a memristor crossbar is time exhaustive. Hence, we propose a neural network-based memristor crossbar modeling method, XBarNet. By transforming memristor crossbar modeling to pixel-to-pixel regression, XBarNet avoids the iterative procedure in the conventional SPICE method, accelerating the runtime significantly. Meanwhile, XBarNet models the interconnect resistance and nonlinear$I-V$effect of memristor crossbars, which minimizes the simulation errors. We first propose a feature extraction method to bridge a memristor crossbar circuit and a neural network. Then, the network based on the convolutional autoencoder architecture is developed and the filter pruning technique is applied onto XBarNet to reduce the runtime computational cost. The experimental result shows our proposed XBarNet achieves over$78\times $runtime speed up and$1.7\times $memory reduction with only 0.28% relative error comparing to the SPICE simulator.

The conventional mapping method between RRAM array and convolutional weights faces two key challenges: 1) nonoptimal energy efficiency and 2) RRAM's temporal variation. To address these challenges, we propose shift and duplicate kernel (SDK) convolutional weight mapping architecture. Each kernel is duplicated multiple times and rearranged on different bitlines in a shifted manner, enabling higher intralayer computational parallelism, and reducing the number of input data loading. Hence, this architecture reduces the computational latency and energy consumption in both forward and backward propagation phases. Furthermore, we have introduced a parallel-window size allocation algorithm and a kernel synchronization method. Our proposed parallel-window size allocation algorithm aims to balance the interlayer pipeline architecture, thus improving the overall energy efficiency and area efficiency. Our proposed kernel synchronization method uses an averaging method to suppress the effect of temporal variation during weight update, enhancing the system's robustness for training. From our experiment results, our proposed architecture achieves ~6.8× area efficiency and ~2.1× energy efficiency over the conventional interlayer pipeline architecture. Significant improvement in classification accuracy by 21.7% under a temporal variation of 1%-5% is achieved during on-chip training task on the Cifar-10 dataset.

The use of deep neural networks in pattern matching has tremendously improved the accuracy of the lithographic hotspot detection, preventing any catastrophic chip failure. In this paper, we propose three data augmentation techniques ("Translation", "Gaussian noise", and "Fill shapes") to deal with the imbalance outlier lithographic hotspot problem and adopt the neural ordinary differential equations networks (Litho-NeuralODE) to improve the detection accuracy. Our architecture uses 28x28 pixel clips to perform the hotspot classification. Experimental result on ICCAD 2012 Contest benchmarks shows that our proposed framework achieves the overall highest accuracy of 98.7% and the lowest misses of 10 on average, outperforming the state-of-the-art works.