Computing-in-Memory (CIM) with ReRAM crossbar arrays accelerates Deep Neural Network (DNN) computations by executing operations directly within memory, which reduces both data movement and energy consumption. Recent studies show that lowering the precision of Analog-to-Digital Converters (ADC) in crossbar peripheral circuits can significantly reduce system area and power overheads at the risk of increasing quantization-induced numerical errors that degrade inference accuracy. This paper proposes a Boundary-Aware Regularized Quantization (BARQ) technique to maintain accuracy in CIM accelerators with low-precision ADCs. BARQ introduces ADC bit-width boundary constraints to regulate model weights during quantization-aware training (QAT), mitigating overflow-induced clipping errors and enhancing unstructured weight sparsity. Additionally, we introduce a novel weight initialization strategy based on Euclidean projection, which minimizes initial quantization error and facilitates faster and more stable convergence. Experiments on the CIFAR-10, CIFAR-100, and ImageNet datasets show that BARQ achieves minimal accuracy loss of only 0.59% even with 3-bit ADCs. Furthermore, by enhancing weight sparsity, BARQ further reduces energy consumption by up to 75% and improves hardware efficiency by 3.79× compared to conventional quantization methods.

This paper proposes a residual amplifier (RA) with high open-loop gain, wide output swing, and integrated auto-zeroing (AZ) functionality. To satisfy the stringent relative gain error requirements of high-precision successive-approximation-register (SAR) analog-to-digital converters (ADCs), the RA employs a three-stage architecture to achieve enhanced open-loop gain while maintaining a broad output voltage range. Stability in the multi-stage design is ensured through the strategic placement of the second and third poles using the complex-pole method. The input stage incorporates a current-reuse technique to double the effective trans-conductance, reducing thermal noise and extending bandwidth without increasing static power consumption. Additionally, an AZ technique is integrated to suppress offset voltage and mitigate low-frequency 1/f noise. Simulated in a 40nm CMOS process, the opamp achieves an open-loop gain exceeding 130dB, and a loop gain of over 101 dB when configured as 61.5× switched-capacitor (SC) RA. The design delivers a bandwidth of 30 MHz, a phase margin greater than 60°, and an input-reference total noise of 14.8 μVrms, with a power consumption of 5.6 mW. These results demonstrate the RA’s capability to meet the demands of high-resolution pipelined SAR ADCs, combining precision, dynamic performance, and power efficiency.

In this paper, a 32kb radiation-hardened (RH) static random access memory (SRAM) chip, named BH55RHSRAM32K, is proposed and fabricated for space applications. The chip is hardened from the view of the circuit level, layout level, and system level and is fabricated using a 55 nm CMOS process design kit with an RH cell library. At the circuit level, the proposed RH-14T SRAM cell and radiation-hardened pre-charged sense amplifier (RH-PCSA) cell adopt a polarity hardening method, making them fully tolerant of single event upset (SEU). At the layout level, the sensitive nodes in the proposed RH-14T SRAM cell and RH-PCSA cell layouts are isolated. Furthermore, the proposed RH-14T SRAM array adopts a bit-interleaved design, effectively reducing single event double upsets (SEDU). At the system level, an error correction coding (ECC) circuit is implemented to enhance SEU tolerance. Experimental results show that the proposed 32kb RH-SRAM chip can not only obtains superior radiation tolerance, i.e., the SEU ≤ 1.1E-11 upsets/bit-day, the SEL > 107.1 MeV⋅cm2/mg, and the TID > 100 Krad(Si), but also a faster access speed of < 10 ns and a lower write power consumption of 14.664 mW in comparison with the related products.

Benefitting from its non-volatility, high speed, low power and inherent radiation hardened characteristic, magnetic random access memory (MRAM) has been used in aerospace and avionic electronics. Owing to its high sensing reliability, precharge differential sense amplifier (PCDSA) has been proposed and widely used in MRAM products. However, such PCDSA is based on the conventional CMOS technology and its sensing result is prone to be affected by the single event upset (SEU) and even the single event double node upset (SEDU) when the CMOS technology node shrinks into the nanometer scale. In this paper, we propose a novel PCDSA to tolerate the SEDU, in which the special three-input C-element that behaves as an inverter when its inputs have the same logic value and holds its previous value when its inputs have the different logic values is employed. By using a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit, hybrid simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can fully tolerate the SEDU when the amount of the deposited charge (Qinj) reaches up to 2 pC. In the worst case where the Qinjis 2 pC, it can achieve a small recover time of 1.3368 ns and low recover energy dissipation of 1.967 pJ with the optimized VDDof 1 V.

Although the magnetic tunnel junction (MTJ) is intrinsically immune to radiation, the read/write operations of magnetic random access memory (MRAM) may be vulnerable to radiation-induced current. In this paper, we investigate the radiation hardening design for spin orbit torque based MRAM (SOT-MRAM). The hardening technique is firstly studied at the device level by optimizing the dimension and magnetic parameters. Then we propose radiation hardening read and write circuits addressing the influence of single event upset (SEU). Based on a physics-based SOT-MTJ compact model and a 65nm CMOS design kit, simulation results show that the proposed MOS-stacked read sensing amplifier and write circuits of six PMOS transistors as a feed-back structure to charge/discharge sensitive nodes can correct soft errors.