Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data.

Farimah R. Poursafaei

dblp:205/7849 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2017
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 77% Embedded and real-time systems · 23%

Topics — the 5 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Embedded and real-time systems › embedded hardware platform
multicore embedded systems
0.312017
NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems · IEEE Trans. Computers 2017
Memory systems
non-volatile memory
0.312017
NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems · IEEE Trans. Computers 2017
Memory systems › memory management
NVM-aware memory management
0.312017
NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems · IEEE Trans. Computers 2017
Memory systems › memory management › memory allocation
page allocation
0.312017
NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems · IEEE Trans. Computers 2017
Memory systems › memory management
memory management unit
0.112017
NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems · IEEE Trans. Computers 2017

Methods — techniques the papers use, named apart from their topics

data partitioning · 0.3access pattern analysis · 0.3
YearPublicationVenuePosition
2017 NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems
abstract
Energy consumption is one of the prominent design constraints of multi-core embedded systems. Since the memory subsystem is responsible for a considerable portion of energy consumption of embedded systems, Non-Volatile Memories (NVMs) have been proposed as a candidate for replacing conventional memories such as SRAM and DRAM. The advantages of NVMs compared to conventional memories are that they consume less leakage power and provide higher density. However, these memories suffer from increased overhead of write operations and limited lifetime. In order to address these issues, researchers have proposed NVM-aware memory management techniques that consider the characteristics of the memories of the system when deciding on the placement of the application data. In systems equipped with memory management unit (MMU), the application data is partitioned into pages during the compile phase and the data is managed at page level during the runtime phase. In this paper we present an NVM-aware data partitioning and mapping technique for multi-core embedded systems equipped with MMU that specifies the placement of the application data based on access pattern of the data and characteristics of the memories. The experimental results show that the proposed technique improves the energy consumption of the system by 28.10 percent on average.
Farimah R. Poursafaei, Mostafa Bazzaz, Alireza Ejlali
IEEE Trans. Computers1