In this study, corner non-functional solder joints were designed as solder joint canaries, and their cycles to failure were compared under four-point bending and thermal cycling tests. A more efficient design and verification method for solder joint canaries was developed. By changing the PCB pad area of the corner solder joints, they were used as canaries for internal functional solder joints, allowing in-situ prediction of internal solder joint failures. To obtain the cycles to failure of solder joint canaries of different sizes, both thermal cycling tests and four-point bending cyclic tests were performed. The four-point bending test provides a more controllable and faster stress loading process. The results show that, compared with the four-point bending test, the thermal cycling test has a longer testing period and shows less distinct regulation effects among different-sized solder joint canaries. To verify the experimental results, a unified creep–plasticity constitutive model coupled with damage was proposed based on a previous model. Using the four-point bending simulation model, the damage evolution during solder joint fatigue was simulated, and the failure behaviors of different-sized solder joint canaries were validated. Further analysis shows that the initial R50 solder joints contain more low-angle grain boundaries and smaller orientation differences compared with the R100 solder joints, resulting in a longer fatigue life. These findings provide important theoretical and methodological support for the efficient design and verification of solder joint canaries.

To satisfy the developmental requirements of applications, such as autonomous driving, high-performance computing, and the Internet of Things (IoT), the integration density, performance, and reliability tradeoff of electronic systems are posing numerous challenges. Prognostics and health management (PHM) using multiple types of sensors can address reliability problems and enhance the functional safety of electronic systems. However, the limited integration density of conventional electronic packaging indicates that functional chips can only replace sensor chips for physical quantity monitoring, without simultaneous functional degradation monitoring and fault identification. This study proposed an integration method that is compatible with front and rear processes to integrate temperature and stress sensors into the power-driven module, that is, fan-out wafer-level packaging technology. First, the temperature and stress sensors are calibrated using a microloading platform and sensitivity consistency is ensured. Second, the temperature inside the module under various working conditions is evaluated using the data obtained by temperature sensors. The stress data inside the micromodule under mechanical loading are obtained through stress sensors. The proposed method can realizein situmonitoring inside advanced packaging and provide considerable data for PHM research.

This article pioneers in-situ monitoring of stress evolution in operational advanced packaging structures through embedded silicon-based piezoresistive sensors. During four-point bending fatigue tests, we discovered a counterintuitive phenomenon: instead of exhibiting cyclic variations, the substrate stress progressively accumulated with loading cycles, eventually reaching saturation. To decipher this anomalous behavior, we developed an enhanced unified creep-plasticity constitutive model that concurrently captures nonlinear deformation mechanisms in solder joints, including simultaneous isotropic/kinematic hardening and strain-rate sensitivity. The model, validated through iterative finite element method (FEM)-sensor data convergence, revealed strain hardening in SAC305 solder joints as the dominant driver of substrate stress accumulation, with <8% deviation from experimental measurements—significantly outperforming conventional Anand models. Microstructural evidence from SEM/EDS further linked Pb particle fragmentation to accumulated inelastic deformation, bridging macro-mechanical responses to microscopic evolution. This article establishes a paradigm for reliability-by-design in next-gen packaging by synergizing embedded sensing with physics-aware constitutive modeling, addressing the critical gap in traditional approaches relying on ex-situ characterization.

Precise static analysis is necessary for an industrial environment to ensure reliability and security, which is usually field-sensitive and inter-procedural. However, it faces the problem of insufficient scale capability when being applied to various industrial environments: (1) Field-sensitive analysis can not assure termination if field accesses are modeled by unbounded access paths; (2) Inter-procedural analysis may lead to path explosion problems because of the unbounded length of call chains. While using longer access paths or call chains can improve precision, the analysis may have poor performance in terms of efficiency. Specifically, an industry-strength method should be scalable enough to face different applications. This paper presents a scalable fault detection method based on the precise access path. Precise access path models a memory location with accurate operations and offsets from a source. Points-to relations of variables are used to refine it. It can differentiate elements of aggregate structures and is more precise than the ordinary access path. Based on the precise access path, we perform an inter-procedural analysis with the help of an intra-procedural analysis and combined function summary. Furthermore, our method is designed backward to detect error handling bugs. Compared with the state-of-the-art tools, our method is more scalable, with higher precision and efficiency on both benchmarks and 11 widely-used applications.

Precise pointer analysis is desired since many program analyses benefit from it both in precision and performance. There are several dimensions of pointer analysis precision, flow sensitivity, context sensitivity, field sensitivity and path sensitivity. The more dimensions a pointer analysis considers, the more accurate its results will be. However, considering all dimensions is difficult because the trade-off between precision and efficiency should be balanced. This paper presents a flow, context, field and quasi path sensitive pointer analysis algorithm for C programs. Our algorithm runs on a control flow automaton, a key structure for our analysis to be flow sensitive. During the analysis process, we use function summaries to get context information. Elements of aggregate structures are handled to improve precision. We collect path conditions to filter unreachable paths and make all points-to relations gated. For efficiency, we propose a multi-entry mechanism. The algorithm is implemented in TsmartGP, which is an extension of CPAchecker. Our algorithm is compared with some state-of-the-art algorithms and TsmartGP is compared with cppcheck and Clang Static Analyzer by detecting uninitialized pointer errors in 13 real-world applications. The experimental results show that our algorithm is more accurate and TsmartGP can find more errors than other tools.

Value flow are widely used in static analysis to detect bugs. Existing techniques usually employ a pointer analysis and generate source sink summaries defined by problem domain, then a solver is invoked to determine whether the path is feasible. However, most of the tools does not provide an easy way for users to find user defined bugs within the same architecture of finding pre-defined bugs. This paper presents VFQL, an expressive query language on value flow graph and the framework to execute the query to find user defined defects. Moreover, VFQL provides a nice GUI to demonstrate the value flow graph and a modeling language to define system libraries or user libraries without code, which further enhances its usability. The experimental results on open benchmarks show that VFQL achieve a competitive performance against other state of art tools. The result of case study conducted on open source program shows that the flexible query and modeling language provide a great support in finding user specified defects.

Static analysis has long prevailed as a promising approach to detect program bugs at an early development process to increase software quality. However, such tools face great challenges to balance the false-positive rate and the false-negative rate in practical use. In this paper, we present VBSAC, a value-based static analyzer for C aiming to improve the precision and recall. In our tool, we employ a pluggable value-based analysis strategy. A memory skeleton recorder is designed to maintain the memory objects as a baseline. While traversing the control flow graph, diverse value-based plug-ins analyze the specific abstract domains and share program information to strengthen the computation. Simultaneously, checkers consume the corresponding analysis results to detect bugs. We also provide a user-friendly web interface to help users audit the bug detection results. Evaluation on two widely-used benchmarks shows that we perform better to state-of-the-art bug detection tools by finding 221-339 more bugs and improving F-Score 9.88%-40.32%.

Precise pointer analysis is desired since it is a core technique to find memory defects. There are several dimensions of pointer analysis precision, flow sensitivity, context sensitivity, field sensitivity and path sensitivity. For static analysis tools utilizing pointer analysis, considering all dimensions is difficult because the trade-off between precision and efficiency should be balanced. This paper presents TsmartGP, a static analysis tool for finding memory defects in C programs with a precise and efficient pointer analysis. The pointer analysis algorithm is flow, context, field, and quasi path sensitive. Control flow automatons are the key structures for our analysis to be flow sensitive. Function summaries are applied to get context information and elements of aggregate structures are handled to improve precision. Path conditions are used to filter unreachable paths. For efficiency, a multi-entry mechanism is proposed. Utilizing the pointer analysis algorithm, we implement a checker in TsmartGP to find uninitialized pointer errors in 13 real-world applications. Cppcheck and Clang Static Analyzer are chosen for comparison. The experimental results show that TsmartGP can find more errors while its accuracy is also higher than Cppcheck and Clang Static Analyzer. The demo video is available at https://youtu.be/IQlshemk6OA.

Combinatorial testing can test software that has various configurations for multiple parameters efficiently. This method is based on a set of test cases that guarantee a certain level of interaction among parameters. Mixed covering array (MCA) can be used to represent a test-suite. Each row of the array corresponds to a test case. In general, a smaller size of MCA does not necessarily imply less testing time. There are certain combinations of parameter values which would take much longer time than other cases. Based on this observation, it is more valuable to construct MCAs that are better in terms of testing effort characterization other than size. We present a method to find cost-aware MCAs. The method contains two steps. First, simulated annealing algorithm is used to get an MCA with a small size. Then we propose a novel nested differential evolution algorithm to improve the solution with its testing effort. The experimental results indicate that our method succeeds in constructing cost-aware MCAs for real-world applications. The testing effort is significantly reduced compared with representative state-of-the-art algorithms.

When analyzing programs using static program analysis, we need to determine the reachability of each possible execution path of the programs. Many static analysis tools collect constraints of each path and use SMT solvers to determine the satisfiability of these constraints. The accumulated computing time can be long if we use SMT solvers too many times. In this paper, we propose a constraint-pattern based method for reachability determination to address the limitation of current approaches. We define some constraint-patterns. For each pattern, a carefully designed constraints solving algorithm is presented. Our method contains two steps. Firstly, we collect some information about the constraints in the program to be analyzed. Then we choose the most suitable algorithm for reachability determination based on the information. Secondly, we apply the algorithm in analysis process to speed up satisfiability checking of path constraints. We implement our method based on CPAchecker, a famous software verification tool. The experimental results on some well-known benchmarks show that, with a moderate accuracy, our method is more efficient in comparison with some state-of-the-art SMT solvers.

To reduce the false positives of static analysis, many tools collect path constraints and integrate SMT solvers to filter unreachable execution paths. However, the accumulated calling and computing of SMT solvers are time and resource consuming. This paper presents TsmartLW, an alternate static analysis tool in which we implement a path constraint solving engine to speed up reachability determination. Within the engine, typical types of constraint-patterns are firstly defined based on an empirical study of a large number of code repositories. For each pattern, a constraint solving algorithm is designed and implemented. For each program, the engine predicts the most suitable strategy and then applies the strategy to solve path constraints. The experimental results on some well-known benchmarks and real-world applications show that TsmartLW is faster than some state-of-the-art static analysis tools. For example, it is 1.32× faster than CPAchecker and our engine is 369× faster than SMT solvers in solving path constraints. The demo video is available at https://www.youtube.com/watch?v=5c3ARhFclHA&t=2s.